clk: sunxi-ng: h6-r: Simplify R_APB1 clock definition (675a6d46) · Commits · 戴 / test

Like the APB0 clock on previous chips, this is a simple single-parent clock with an M divider. Use the equivalent helper macro instead of writing out the whole clock description manually. Signed-off-by:

Samuel Holland <samuel@sholland.org> Signed-off-by:

Maxime Ripard <maxime@cerno.tech>

drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c

+1 −11

Original line number	Diff line number	Diff line
		@@ -51,17 +51,7 @@ static struct ccu_div ar100_clk = {

		static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);

		static struct ccu_div r_apb1_clk = {
		.div = _SUNXI_CCU_DIV(0, 2),

		.common = {
		.reg = 0x00c,
		.hw.init = CLK_HW_INIT("r-apb1",
		"r-ahb",
		&ccu_div_ops,
		0),
		},
		};
		static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);

		static struct ccu_div r_apb2_clk = {
		.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),

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