Unverified Commit 47d64fef authored by Samuel Holland's avatar Samuel Holland Committed by Maxime Ripard
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clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock 



According to the BSP source code, the APB0 clock on the H3 and H5 has a
normal M divider, not a power-of-two divider. This matches the hardware
in the A83T (as described in both the BSP source code and the manual).
Since the A83T and H3/A64 clocks are actually the same, we can merge the
definitions.

Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
parent c7b30526

drivers/clk/sunxi-ng/ccu-sun8i-r.c

+3 −18
Original line number Diff line number Diff line
@@ -51,19 +51,7 @@ static struct ccu_div ar100_clk = { 


static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0);



static struct ccu_div apb0_clk = {

	.div		= _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),



	.common		= {

		.reg		= 0x0c,

		.hw.init	= CLK_HW_INIT_HW("apb0",

						 &ahb0_clk.hw,

						 &ccu_div_ops,

						 0),

	},

};



static SUNXI_CCU_M(a83t_apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);

static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);



/*

 * Define the parent as an array that can be reused to save space
@@ -127,7 +115,7 @@ static struct ccu_mp a83t_ir_clk = { 


static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {

	&ar100_clk.common,

	&a83t_apb0_clk.common,

	&apb0_clk.common,

	&apb0_pio_clk.common,

	&apb0_ir_clk.common,

	&apb0_timer_clk.common,
@@ -167,7 +155,7 @@ static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = { 
	.hws	= {

		[CLK_AR100]		= &ar100_clk.common.hw,

		[CLK_AHB0]		= &ahb0_clk.hw,

		[CLK_APB0]		= &a83t_apb0_clk.common.hw,

		[CLK_APB0]		= &apb0_clk.common.hw,

		[CLK_APB0_PIO]		= &apb0_pio_clk.common.hw,

		[CLK_APB0_IR]		= &apb0_ir_clk.common.hw,

		[CLK_APB0_TIMER]	= &apb0_timer_clk.common.hw,
@@ -282,9 +270,6 @@ static void __init sunxi_r_ccu_init(struct device_node *node, 


static void __init sun8i_a83t_r_ccu_setup(struct device_node *node)

{

	/* Fix apb0 bus gate parents here */

	apb0_gate_parent[0] = &a83t_apb0_clk.common.hw;



	sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc);

}

CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu",

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