Commit 67296ad9 authored by Jitendra Bhivare's avatar Jitendra Bhivare Committed by Martin K. Petersen
Browse files

be2iscsi: Use macros for MCC WRB and CQE fields 



Rename mcc_numtag to mcc_tag_status.  MCC CQE status is processed using
macros already defined in be_cmds.h.

Add MCC_Q_WRB_ and MCC_Q_CMD_TAG_MASK macros to map to already defined
CQE_STATUS_ macros to be consistent when posting MCC.

Signed-off-by: default avatarJitendra Bhivare <jitendra.bhivare@broadcom.com>
Reviewed-by: default avatarJohannes Thumshirn <jthumshirn@suse.de>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 9c890a79

drivers/scsi/be2iscsi/be.h

+7 −1
Original line number Diff line number Diff line
@@ -135,7 +135,7 @@ struct be_ctrl_info { 


	wait_queue_head_t mcc_wait[MAX_MCC_CMD + 1];

	unsigned int mcc_tag[MAX_MCC_CMD];

	unsigned int mcc_numtag[MAX_MCC_CMD + 1];

	unsigned int mcc_tag_status[MAX_MCC_CMD + 1];

	unsigned short mcc_alloc_index;

	unsigned short mcc_free_index;

	unsigned int mcc_tag_available;
@@ -145,6 +145,12 @@ struct be_ctrl_info { 


#include "be_cmds.h"



/* WRB index mask for MCC_Q_LEN queue entries */

#define MCC_Q_WRB_IDX_MASK	CQE_STATUS_WRB_MASK

#define MCC_Q_WRB_IDX_SHIFT	CQE_STATUS_WRB_SHIFT

/* TAG is from 1...MAX_MCC_CMD, MASK includes MAX_MCC_CMD */

#define MCC_Q_CMD_TAG_MASK	((MAX_MCC_CMD << 1) - 1)



#define PAGE_SHIFT_4K 12

#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)

#define mcc_timeout		120000 /* 12s timeout */

drivers/scsi/be2iscsi/be_cmds.c

+21 −19
Original line number Diff line number Diff line
@@ -125,7 +125,7 @@ unsigned int alloc_mcc_tag(struct beiscsi_hba *phba) 
	if (phba->ctrl.mcc_tag_available) {

		tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index];

		phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0;

		phba->ctrl.mcc_numtag[tag] = 0;

		phba->ctrl.mcc_tag_status[tag] = 0;

		phba->ctrl.ptag_state[tag].tag_state = 0;

	}

	if (tag) {
@@ -157,7 +157,7 @@ int beiscsi_mccq_compl(struct beiscsi_hba *phba, 
		struct be_dma_mem *mbx_cmd_mem)

{

	int rc = 0;

	uint32_t mcc_tag_response;

	uint32_t mcc_tag_status;

	uint16_t status = 0, addl_status = 0, wrb_num = 0;

	struct be_mcc_wrb *temp_wrb;

	struct be_cmd_req_hdr *mbx_hdr;
@@ -172,7 +172,7 @@ int beiscsi_mccq_compl(struct beiscsi_hba *phba, 
	/* wait for the mccq completion */

	rc = wait_event_interruptible_timeout(

				phba->ctrl.mcc_wait[tag],

				phba->ctrl.mcc_numtag[tag],

				phba->ctrl.mcc_tag_status[tag],

				msecs_to_jiffies(

				BEISCSI_HOST_MBX_TIMEOUT));

	/**
@@ -209,15 +209,15 @@ int beiscsi_mccq_compl(struct beiscsi_hba *phba, 
	}



	rc = 0;

	mcc_tag_response = phba->ctrl.mcc_numtag[tag];

	status = (mcc_tag_response & CQE_STATUS_MASK);

	addl_status = ((mcc_tag_response & CQE_STATUS_ADDL_MASK) >>

	mcc_tag_status = phba->ctrl.mcc_tag_status[tag];

	status = (mcc_tag_status & CQE_STATUS_MASK);

	addl_status = ((mcc_tag_status & CQE_STATUS_ADDL_MASK) >>

			CQE_STATUS_ADDL_SHIFT);



	if (mbx_cmd_mem) {

		mbx_hdr = (struct be_cmd_req_hdr *)mbx_cmd_mem->va;

	} else {

		wrb_num = (mcc_tag_response & CQE_STATUS_WRB_MASK) >>

		wrb_num = (mcc_tag_status & CQE_STATUS_WRB_MASK) >>

			   CQE_STATUS_WRB_SHIFT;

		temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num);

		mbx_hdr = embedded_payload(temp_wrb);
@@ -257,7 +257,7 @@ int beiscsi_mccq_compl(struct beiscsi_hba *phba, 
void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag)

{

	spin_lock(&ctrl->mcc_lock);

	tag = tag & 0x000000FF;

	tag = tag & MCC_Q_CMD_TAG_MASK;

	ctrl->mcc_tag[ctrl->mcc_free_index] = tag;

	if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1))

		ctrl->mcc_free_index = 0;
@@ -334,10 +334,11 @@ int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl, 
	struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);

	u16 compl_status, extd_status;

	struct be_dma_mem *tag_mem;

	unsigned short tag;

	unsigned int tag, wrb_idx;



	be_dws_le_to_cpu(compl, 4);

	tag = (compl->tag0 & 0x000000FF);

	tag = (compl->tag0 & MCC_Q_CMD_TAG_MASK);

	wrb_idx = (compl->tag0 & CQE_STATUS_WRB_MASK) >> CQE_STATUS_WRB_SHIFT;



	if (!test_bit(MCC_TAG_STATE_RUNNING,

		      &ctrl->ptag_state[tag].tag_state)) {
@@ -367,16 +368,17 @@ int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl, 


	compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &

		       CQE_STATUS_COMPL_MASK;

	/* The ctrl.mcc_numtag[tag] is filled with

	extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &

		      CQE_STATUS_EXTD_MASK;

	/* The ctrl.mcc_tag_status[tag] is filled with

	 * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,

	 * [7:0] = compl_status

	 */

	extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &

					CQE_STATUS_EXTD_MASK;

	ctrl->mcc_numtag[tag]  = 0x80000000;

	ctrl->mcc_numtag[tag] |= (compl->tag0 & 0x00FF0000);

	ctrl->mcc_numtag[tag] |= (extd_status & 0x000000FF) << 8;

	ctrl->mcc_numtag[tag] |= (compl_status & 0x000000FF);

	ctrl->mcc_tag_status[tag] = CQE_VALID_MASK;

	ctrl->mcc_tag_status[tag] |= (wrb_idx << CQE_STATUS_WRB_SHIFT);

	ctrl->mcc_tag_status[tag] |= (extd_status << CQE_STATUS_ADDL_SHIFT) &

				     CQE_STATUS_ADDL_MASK;

	ctrl->mcc_tag_status[tag] |= (compl_status & CQE_STATUS_MASK);



	/* write ordering implied in wake_up_interruptible */

	clear_bit(MCC_TAG_STATE_RUNNING, &ctrl->ptag_state[tag].tag_state);
@@ -844,7 +846,7 @@ struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba) 
	WARN_ON(atomic_read(&mccq->used) >= mccq->len);

	wrb = queue_head_node(mccq);

	memset(wrb, 0, sizeof(*wrb));

	wrb->tag0 = (mccq->head & 0x000000FF) << 16;

	wrb->tag0 = (mccq->head << MCC_Q_WRB_IDX_SHIFT) & MCC_Q_WRB_IDX_MASK;

	queue_head_inc(mccq);

	atomic_inc(&mccq->used);

	return wrb;

drivers/scsi/be2iscsi/be_cmds.h

+7 −6
Original line number Diff line number Diff line
@@ -61,12 +61,13 @@ struct be_mcc_wrb { 
#define CQE_STATUS_COMPL_MASK	0xFFFF

#define CQE_STATUS_COMPL_SHIFT	0		/* bits 0 - 15 */

#define CQE_STATUS_EXTD_MASK	0xFFFF

#define CQE_STATUS_EXTD_SHIFT 16		/* bits 0 - 15 */

#define CQE_STATUS_EXTD_SHIFT	16		/* bits 31 - 16 */

#define CQE_STATUS_ADDL_MASK	0xFF00

#define CQE_STATUS_ADDL_SHIFT	8

#define CQE_STATUS_MASK		0xFF

#define CQE_STATUS_ADDL_SHIFT	0x08

#define CQE_STATUS_WRB_MASK	0xFF0000

#define CQE_STATUS_WRB_SHIFT	16



#define BEISCSI_HOST_MBX_TIMEOUT (110 * 1000)

#define BEISCSI_FW_MBX_TIMEOUT	100

drivers/scsi/be2iscsi/be_main.c

+6 −5
Original line number Diff line number Diff line
@@ -5241,11 +5241,12 @@ static int beiscsi_bsg_request(struct bsg_job *job) 


		rc = wait_event_interruptible_timeout(

					phba->ctrl.mcc_wait[tag],

					phba->ctrl.mcc_numtag[tag],

					phba->ctrl.mcc_tag_status[tag],

					msecs_to_jiffies(

					BEISCSI_HOST_MBX_TIMEOUT));

		extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;

		status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;

		extd_status = (phba->ctrl.mcc_tag_status[tag] &

			       CQE_STATUS_ADDL_MASK) >> CQE_STATUS_ADDL_SHIFT;

		status = phba->ctrl.mcc_tag_status[tag] & CQE_STATUS_MASK;

		free_mcc_tag(&phba->ctrl, tag);

		resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;

		sg_copy_from_buffer(job->reply_payload.sg_list,
@@ -5580,7 +5581,7 @@ static void beiscsi_eeh_resume(struct pci_dev *pdev) 
	for (i = 0; i < MAX_MCC_CMD; i++) {

		init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);

		phba->ctrl.mcc_tag[i] = i + 1;

		phba->ctrl.mcc_numtag[i + 1] = 0;

		phba->ctrl.mcc_tag_status[i + 1] = 0;

		phba->ctrl.mcc_tag_available++;

	}
@@ -5739,7 +5740,7 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev, 
	for (i = 0; i < MAX_MCC_CMD; i++) {

		init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);

		phba->ctrl.mcc_tag[i] = i + 1;

		phba->ctrl.mcc_numtag[i + 1] = 0;

		phba->ctrl.mcc_tag_status[i + 1] = 0;

		phba->ctrl.mcc_tag_available++;

		memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0,

		       sizeof(struct be_dma_mem));

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