Commit 67266c10 authored by Jiri Olsa's avatar Jiri Olsa Committed by Ingo Molnar
Browse files

perf/x86/intel: Add generic branch tracing check to intel_pmu_has_bts() 



Currently we check the branch tracing only by checking for the
PERF_COUNT_HW_BRANCH_INSTRUCTIONS event of PERF_TYPE_HARDWARE
type. But we can define the same event with the PERF_TYPE_RAW
type.

Changing the intel_pmu_has_bts() code to check on event's final
hw config value, so both HW types are covered.

Adding unlikely to intel_pmu_has_bts() condition calls, because
it was used in the original code in intel_bts_constraints.

Signed-off-by: default avatarJiri Olsa <jolsa@kernel.org>
Acked-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Cc: <stable@vger.kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/20181121101612.16272-2-jolsa@kernel.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent ed6101bb

arch/x86/events/intel/core.c

+3 −14
Original line number Diff line number Diff line
@@ -2474,16 +2474,7 @@ done: 
static struct event_constraint *

intel_bts_constraints(struct perf_event *event)

{

	struct hw_perf_event *hwc = &event->hw;

	unsigned int hw_event, bts_event;



	if (event->attr.freq)

		return NULL;



	hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;

	bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);



	if (unlikely(hw_event == bts_event && hwc->sample_period == 1))

	if (unlikely(intel_pmu_has_bts(event)))

		return &bts_constraint;



	return NULL;
@@ -3105,10 +3096,8 @@ static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 
static int intel_pmu_bts_config(struct perf_event *event)

{

	struct perf_event_attr *attr = &event->attr;

	struct hw_perf_event *hwc = &event->hw;



	if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&

	    !attr->freq && hwc->sample_period == 1) {

	if (unlikely(intel_pmu_has_bts(event))) {

		/* BTS is not supported by this architecture. */

		if (!x86_pmu.bts_active)

			return -EOPNOTSUPP;
@@ -3170,7 +3159,7 @@ static int intel_pmu_hw_config(struct perf_event *event) 
		/*

		 * BTS is set up earlier in this path, so don't account twice

		 */

		if (!intel_pmu_has_bts(event)) {

		if (!unlikely(intel_pmu_has_bts(event))) {

			/* disallow lbr if conflicting events are present */

			if (x86_add_exclusive(x86_lbr_exclusive_lbr))

				return -EBUSY;

arch/x86/events/perf_event.h

+9 −4
Original line number Diff line number Diff line
@@ -859,11 +859,16 @@ static inline int amd_pmu_init(void) 


static inline bool intel_pmu_has_bts(struct perf_event *event)

{

	if (event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&

	    !event->attr.freq && event->hw.sample_period == 1)

		return true;

	struct hw_perf_event *hwc = &event->hw;

	unsigned int hw_event, bts_event;



	if (event->attr.freq)

		return false;



	hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;

	bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);



	return hw_event == bts_event && hwc->sample_period == 1;

}



int intel_pmu_save_and_restart(struct perf_event *event);

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