Commit ed6101bb authored by Jiri Olsa's avatar Jiri Olsa Committed by Ingo Molnar
Browse files

perf/x86/intel: Move branch tracing setup to the Intel-specific source file 



Moving branch tracing setup to Intel core object into separate
intel_pmu_bts_config function, because it's Intel specific.

Suggested-by: default avatarPeter Zijlstra <peterz@infradead.org>
Signed-off-by: default avatarJiri Olsa <jolsa@kernel.org>
Acked-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Cc: <stable@vger.kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/20181121101612.16272-1-jolsa@kernel.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent b1a9d7b0

arch/x86/events/core.c

+0 −20
Original line number Diff line number Diff line
@@ -438,26 +438,6 @@ int x86_setup_perfctr(struct perf_event *event) 
	if (config == -1LL)

		return -EINVAL;



	/*

	 * Branch tracing:

	 */

	if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&

	    !attr->freq && hwc->sample_period == 1) {

		/* BTS is not supported by this architecture. */

		if (!x86_pmu.bts_active)

			return -EOPNOTSUPP;



		/* BTS is currently only allowed for user-mode. */

		if (!attr->exclude_kernel)

			return -EOPNOTSUPP;



		/* disallow bts if conflicting events are present */

		if (x86_add_exclusive(x86_lbr_exclusive_lbr))

			return -EBUSY;



		event->destroy = hw_perf_lbr_event_destroy;

	}



	hwc->config |= config;



	return 0;

arch/x86/events/intel/core.c

+40 −1
Original line number Diff line number Diff line
@@ -3102,10 +3102,49 @@ static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 
	return flags;

}



static int intel_pmu_bts_config(struct perf_event *event)

{

	struct perf_event_attr *attr = &event->attr;

	struct hw_perf_event *hwc = &event->hw;



	if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&

	    !attr->freq && hwc->sample_period == 1) {

		/* BTS is not supported by this architecture. */

		if (!x86_pmu.bts_active)

			return -EOPNOTSUPP;



		/* BTS is currently only allowed for user-mode. */

		if (!attr->exclude_kernel)

			return -EOPNOTSUPP;



		/* disallow bts if conflicting events are present */

		if (x86_add_exclusive(x86_lbr_exclusive_lbr))

			return -EBUSY;



		event->destroy = hw_perf_lbr_event_destroy;

	}



	return 0;

}



static int core_pmu_hw_config(struct perf_event *event)

{

	int ret = x86_pmu_hw_config(event);



	if (ret)

		return ret;



	return intel_pmu_bts_config(event);

}



static int intel_pmu_hw_config(struct perf_event *event)

{

	int ret = x86_pmu_hw_config(event);



	if (ret)

		return ret;



	ret = intel_pmu_bts_config(event);

	if (ret)

		return ret;
@@ -3600,7 +3639,7 @@ static __initconst const struct x86_pmu core_pmu = { 
	.enable_all		= core_pmu_enable_all,

	.enable			= core_pmu_enable_event,

	.disable		= x86_pmu_disable_event,

	.hw_config		= x86_pmu_hw_config,

	.hw_config		= core_pmu_hw_config,

	.schedule_events	= x86_schedule_events,

	.eventsel		= MSR_ARCH_PERFMON_EVENTSEL0,

	.perfctr		= MSR_ARCH_PERFMON_PERFCTR0,

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