Commit 66ffb915 authored by Jonathan Marek's avatar Jonathan Marek Committed by Rob Clark
Browse files

drm/msm/a6xx: add A640/A650 hwcg 



Initialize hardware clock-gating registers on A640 and A650 GPUs.

At least for A650, this solves some performance issues.

Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent b1c53a2a

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+114 −3
Original line number Diff line number Diff line
@@ -263,6 +263,112 @@ const struct adreno_reglist a630_hwcg[] = { 
	{},

};



const struct adreno_reglist a640_hwcg[] = {

	{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},

	{REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},

	{REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},

	{REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},

	{REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},

	{REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},

	{REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},

	{REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},

	{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},

	{REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},

	{REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},

	{REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},

	{REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},

	{REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},

	{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},

	{REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},

	{REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

	{REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},

	{REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},

	{REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},

	{REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{REG_A6XX_RBBM_ISDB_CNT, 0x00000182},

	{REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},

	{REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},

	{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},

	{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},

	{},

};



const struct adreno_reglist a650_hwcg[] = {

	{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},

	{REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},

	{REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},

	{REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},

	{REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},

	{REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},

	{REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},

	{REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},

	{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},

	{REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},

	{REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},

	{REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},

	{REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},

	{REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},

	{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},

	{REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},

	{REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

	{REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},

	{REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},

	{REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},

	{REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},

	{REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{REG_A6XX_RBBM_ISDB_CNT, 0x00000182},

	{REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},

	{REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},

	{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},

	{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},

	{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},

	{},

};



static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -270,15 +376,20 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 
	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

	const struct adreno_reglist *reg;

	unsigned int i;

	u32 val;

	u32 val, clock_cntl_on;



	if (!adreno_gpu->info->hwcg)

		return;



	if (adreno_is_a630(adreno_gpu))

		clock_cntl_on = 0x8aa8aa02;

	else

		clock_cntl_on = 0x8aa8aa82;



	val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);



	/* Don't re-program the registers if they are already correct */

	if ((!state && !val) || (state && (val == 0x8aa8aa02)))

	if ((!state && !val) || (state && (val == clock_cntl_on)))

		return;



	/* Disable SP clock before programming HWCG registers */
@@ -290,7 +401,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 
	/* Enable SP clock */

	gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);



	gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? 0x8aa8aa02 : 0);

	gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);

}



static void a6xx_set_ubwc_config(struct msm_gpu *gpu)

drivers/gpu/drm/msm/adreno/adreno_device.c

+2 −0
Original line number Diff line number Diff line
@@ -213,6 +213,7 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init = a6xx_gpu_init,

		.zapfw = "a640_zap.mdt",

		.hwcg = a640_hwcg,

	}, {

		.rev = ADRENO_REV(6, 5, 0, ANY_ID),

		.revn = 650,
@@ -225,6 +226,7 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init = a6xx_gpu_init,

		.zapfw = "a650_zap.mdt",

		.hwcg = a650_hwcg,

	},

};

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+1 −1
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ struct adreno_reglist { 
	u32 value;

};



extern const struct adreno_reglist a630_hwcg[];

extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[];



struct adreno_info {

	struct adreno_rev rev;

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