drm/msm/a6xx: hwcg tables in gpulist (b1c53a2a) · Commits · 戴 / test

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+11 −14

Original line number	Diff line number	Diff line
		@@ -154,10 +154,7 @@ static void a6xx_submit(struct msm_gpu gpu, struct msm_gem_submit submit,
		a6xx_flush(gpu, ring);
		}

		static const struct {
		u32 offset;
		u32 value;
		} a6xx_hwcg[] = {
		const struct adreno_reglist a630_hwcg[] = {
		{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
		{REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
		{REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
		@@ -262,7 +259,8 @@ static const struct {
		{REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
		{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
		{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
		{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}
		{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
		{},
		};

		static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
		@@ -270,9 +268,13 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
		struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
		struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
		struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
		const struct adreno_reglist *reg;
		unsigned int i;
		u32 val;

		if (!adreno_gpu->info->hwcg)
		return;

		val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);

		/* Don't re-program the registers if they are already correct */
		@@ -282,9 +284,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
		/* Disable SP clock before programming HWCG registers */
		gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);

		for (i = 0; i < ARRAY_SIZE(a6xx_hwcg); i++)
		gpu_write(gpu, a6xx_hwcg[i].offset,
		state ? a6xx_hwcg[i].value : 0);
		for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
		gpu_write(gpu, reg->offset, state ? reg->value : 0);

		/* Enable SP clock */
		gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
		@@ -440,11 +441,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
		gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
		gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);

		/*
		* enable hardware clockgating
		* For now enable clock gating only for a630
		*/
		if (adreno_is_a630(adreno_gpu))
		/* enable hardware clockgating */
		a6xx_set_hwcg(gpu, true);

		/* VBIF/GBIF start*/

drivers/gpu/drm/msm/adreno/adreno_device.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -200,6 +200,7 @@ static const struct adreno_info gpulist[] = {
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
		.init = a6xx_gpu_init,
		.zapfw = "a630_zap.mdt",
		.hwcg = a630_hwcg,
		}, {
		.rev = ADRENO_REV(6, 4, 0, ANY_ID),
		.revn = 640,

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+8 −0

Original line number	Diff line number	Diff line
		@@ -68,6 +68,13 @@ struct adreno_gpu_funcs {
		int (get_timestamp)(struct msm_gpu gpu, uint64_t *value);
		};

		struct adreno_reglist {
		u32 offset;
		u32 value;
		};

		extern const struct adreno_reglist a630_hwcg[];

		struct adreno_info {
		struct adreno_rev rev;
		uint32_t revn;
		@@ -78,6 +85,7 @@ struct adreno_info {
		struct msm_gpu (init)(struct drm_device *dev);
		const char *zapfw;
		u32 inactive_period;
		const struct adreno_reglist *hwcg;
		};

		const struct adreno_info *adreno_info(struct adreno_rev rev);

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