Commit 6644fddf authored by Chao Xie's avatar Chao Xie Committed by Stephen Boyd
Browse files

clk: mmp: Fix the wrong factor table for uart PLL 



The suggested value in the mmp2 manual is wrong.
There are only 13 bits for numerator, but some suggested
value has 14 bits.
Fix the factor tabled and remove the unused items.

Signed-off-by: default avatarChao Xie <chao.xie@marvell.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent a35247c6

drivers/clk/mmp/clk-mmp2.c

+1 −3
Original line number Diff line number Diff line
@@ -63,10 +63,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = { 
};



static struct mmp_clk_factor_tbl uart_factor_tbl[] = {

	{.num = 14634, .den = 2165},	/*14.745MHZ */

	{.num = 8125, .den = 1536},	/*14.745MHZ */

	{.num = 3521, .den = 689},	/*19.23MHZ */

	{.num = 9679, .den = 5728},	/*58.9824MHZ */

	{.num = 15850, .den = 9451},	/*59.429MHZ */

};



static const char *uart_parent[] = {"uart_pll", "vctcxo"};

drivers/clk/mmp/clk-of-mmp2.c

+1 −3
Original line number Diff line number Diff line
@@ -98,10 +98,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = { 
};



static struct mmp_clk_factor_tbl uart_factor_tbl[] = {

	{.num = 14634, .den = 2165},	/*14.745MHZ */

	{.num = 8125, .den = 1536},	/*14.745MHZ */

	{.num = 3521, .den = 689},	/*19.23MHZ */

	{.num = 9679, .den = 5728},	/*58.9824MHZ */

	{.num = 15850, .den = 9451},	/*59.429MHZ */

};



static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit)

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