Commit a35247c6 authored by Chao Xie's avatar Chao Xie Committed by Stephen Boyd
Browse files

clk: mmp: add fixed clock UBS_PLL for pxa910/pxa168 



USB will drive clock from USB_PLL.

Signed-off-by: default avatarChao Xie <chao.xie@marvell.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent ae8d4048

drivers/clk/mmp/clk-of-pxa168.c

+1 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = { 
	{PXA168_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},

	{PXA168_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},

	{PXA168_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},

	{PXA168_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},

};



static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {

drivers/clk/mmp/clk-of-pxa910.c

+1 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = { 
	{PXA910_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},

	{PXA910_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},

	{PXA910_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},

	{PXA910_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},

};



static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {

include/dt-bindings/clock/marvell,pxa168.h

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#define PXA168_CLK_PLL1_2_1_5		19

#define PXA168_CLK_PLL1_3_16		20

#define PXA168_CLK_UART_PLL		27

#define PXA168_CLK_USB_PLL		28



/* apb periphrals */

#define PXA168_CLK_TWSI0		60

include/dt-bindings/clock/marvell,pxa910.h

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#define PXA910_CLK_PLL1_2_1_5		19

#define PXA910_CLK_PLL1_3_16		20

#define PXA910_CLK_UART_PLL		27

#define PXA910_CLK_USB_PLL		28



/* apb periphrals */

#define PXA910_CLK_TWSI0		60

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