Unverified Commit 6630aad7 authored Mar 14, 2019 by Icenowy Zheng Committed by Maxime Ripard Mar 18, 2019

clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset



The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.

Fix this problem.

Fixes: 0380126e ("clk: sunxi-ng: add support for suniv F1C100s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

parent ab65e04d

drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -240,7 +240,7 @@ static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
		/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */

		static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
		0x0cc, BIT(8), 0);
		0x0cc, BIT(1), 0);

		static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
		0x100, BIT(0), 0);

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