Unverified Commit ab65e04d authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Maxime Ripard
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clk: sunxi-ng: Allow DE clock to set parent rate 



DE2/DE3 mixers have to run at specific frequency in order to work
optimally. This wasn't actually possible for some SoCs because "de"
clock wasn't allowed to adjust parent rate.

Add CLK_SET_RATE_PARENT flag to all "de" clocks which didn't have it
yet.

Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent 9e98c678

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+2 −1
Original line number Diff line number Diff line
@@ -531,7 +531,8 @@ static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", 


static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };

static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,

				 0x104, 0, 4, 24, 3, BIT(31), 0);

				 0x104, 0, 4, 24, 3, BIT(31),

				 CLK_SET_RATE_PARENT);



static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };

static const u8 tcon0_table[] = { 0, 2, };

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

+1 −1
Original line number Diff line number Diff line
@@ -266,7 +266,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600, 
				       0, 4,	/* M */

				       24, 1,	/* mux */

				       BIT(31),	/* gate */

				       0);

				       CLK_SET_RATE_PARENT);



static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",

		      0x60c, BIT(0), 0);

drivers/clk/sunxi-ng/ccu-sun8i-v3s.c

+2 −1
Original line number Diff line number Diff line
@@ -325,7 +325,8 @@ static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram", 


static const char * const de_parents[] = { "pll-video", "pll-periph0" };

static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,

				 0x104, 0, 4, 24, 2, BIT(31), 0);

				 0x104, 0, 4, 24, 2, BIT(31),

				 CLK_SET_RATE_PARENT);



static const char * const tcon_parents[] = { "pll-video" };

static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,

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