+34
−0
+23
−23
+47
−49
Loading
Gitlab 现已全面支持 git over ssh 与 git over https。通过 HTTPS 访问请配置带有 read_repository / write_repository 权限的 Personal access token。通过 SSH 端口访问请使用 22 端口或 13389 端口。如果使用CAS注册了账户但不知道密码,可以自行至设置中更改;如有其他问题,请发邮件至 service@cra.moe 寻求协助。
arm64: soc: ZynqMP SoC changes for v5.11 v2 - Small alignments in Xilinx Firmware driver - Exposing syscon interface for VCU driver * tag 'zynqmp-soc-for-v5.11-v2' of https://github.com/Xilinx/linux-xlnx: firmware: xilinx: Properly align function parameter firmware: xilinx: Add a blank line after function declaration firmware: xilinx: Remove additional newline firmware: xilinx: Fix kernel-doc warnings firmware: xlnx-zynqmp: fix compilation warning soc: xilinx: vcu: add missing register NUM_CORE soc: xilinx: vcu: use vcu-settings syscon registers dt-bindings: soc: xlnx: extract xlnx, vcu-settings to separate binding soc: xilinx: vcu: drop useless success message Link: https://lore.kernel.org/r/71d38756-4456-29fc-26a3-341e1d09aafe@monstr.eu Signed-off-by:Arnd Bergmann <arnd@arndb.de>
CRA Git | Maintained and supported by SUSTech CRA and CCSE