Merge tag 'memory-controller-drv-tegra-5.11-3' of...

- #interconnect-cells : Should be 0.

- operating-points-v2: See ../bindings/opp/opp.txt for details.

For each opp entry in 'operating-points-v2' table:

- opp-supported-hw: One bitfield indicating SoC process ID mask

	A bitwise AND is performed against this value and if any bit

	matches, the OPP gets enabled.

Optional properties:

- core-supply: Phandle of voltage regulator of the SoC "core" power domain.

	tristate "NVIDIA Tegra30 External Memory Controller driver"

	default y

	depends on TEGRA_MC && ARCH_TEGRA_3x_SOC

	select PM_OPP

	help

	  This driver is for the External Memory Controller (EMC) found on

	  Tegra30 chips. The EMC controls the external DRAM on the board.

static int tegra_emc_opp_table_init(struct tegra_emc *emc)

{

	struct opp_table *reg_opp_table = NULL, *clk_opp_table;

	const char *rname = "core";

	u32 hw_version = BIT(tegra_sku_info.soc_process_id);

	struct opp_table *clk_opp_table, *hw_opp_table;

	int err;

	/*

	 * Legacy device-trees don't have OPP table and EMC driver isn't

	 * useful in this case.

	 */

	if (!device_property_present(emc->dev, "operating-points-v2")) {

		dev_err(emc->dev,

			"OPP table not found, please update your device tree\n");

		return -ENODEV;

	}

	/* voltage scaling is optional */

	if (device_property_present(emc->dev, "core-supply")) {

		reg_opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1);

		if (IS_ERR(reg_opp_table))

			return dev_err_probe(emc->dev, PTR_ERR(reg_opp_table),

					     "failed to set OPP regulator\n");

	}

	clk_opp_table = dev_pm_opp_set_clkname(emc->dev, NULL);

	err = PTR_ERR_OR_ZERO(clk_opp_table);

	if (err) {

		dev_err(emc->dev, "failed to set OPP clk: %d\n", err);

		goto put_reg_table;

		return err;

	}

	hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);

	err = PTR_ERR_OR_ZERO(hw_opp_table);

	if (err) {

		dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);

		goto put_clk_table;

	}

	err = dev_pm_opp_of_add_table(emc->dev);

	if (err) {

		if (err == -ENODEV)

			dev_err(emc->dev, "OPP table not found, please update your device tree\n");

		else

			dev_err(emc->dev, "failed to add OPP table: %d\n", err);

		goto put_clk_table;

		goto put_hw_table;

	}

	dev_info(emc->dev, "current clock rate %lu MHz\n",

		 clk_get_rate(emc->clk) / 1000000);

	dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",

		 hw_version, clk_get_rate(emc->clk) / 1000000);

	/* first dummy rate-set initializes voltage state */

	err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));

remove_table:

	dev_pm_opp_of_remove_table(emc->dev);

put_hw_table:

	dev_pm_opp_put_supported_hw(hw_opp_table);

put_clk_table:

	dev_pm_opp_put_clkname(clk_opp_table);

put_reg_table:

	if (reg_opp_table)

		dev_pm_opp_put_regulators(reg_opp_table);

	return err;

}

#include <linux/debugfs.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/interconnect-provider.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/iopoll.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/mutex.h>

#include <linux/of_platform.h>

#include <linux/platform_device.h>

#include <linux/pm_opp.h>

#include <linux/slab.h>

#include <linux/sort.h>

#include <linux/types.h>

#include <soc/tegra/common.h>

#include <soc/tegra/fuse.h>

#include "mc.h"

	bool emc_cfg_dyn_self_ref;

};

enum emc_rate_request_type {

	EMC_RATE_DEBUG,

	EMC_RATE_ICC,

	EMC_RATE_TYPE_MAX,

};

struct emc_rate_request {

	unsigned long min_rate;

	unsigned long max_rate;

};

struct tegra_emc {

	struct device *dev;

	struct tegra_mc *mc;

	struct icc_provider provider;

	struct notifier_block clk_nb;

	struct clk *clk;

	void __iomem *regs;

		unsigned long min_rate;

		unsigned long max_rate;

	} debugfs;

	/*

	 * There are multiple sources in the EMC driver which could request

	 * a min/max clock rate, these rates are contained in this array.

	 */

	struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];

	/* protect shared rate-change code path */

	struct mutex rate_lock;

};

static int emc_seq_update_timing(struct tegra_emc *emc)

	return timing->rate;

}

static void tegra_emc_rate_requests_init(struct tegra_emc *emc)

{

	unsigned int i;

	for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {

		emc->requested_rate[i].min_rate = 0;

		emc->requested_rate[i].max_rate = ULONG_MAX;

	}

}

static int emc_request_rate(struct tegra_emc *emc,

			    unsigned long new_min_rate,

			    unsigned long new_max_rate,

			    enum emc_rate_request_type type)

{

	struct emc_rate_request *req = emc->requested_rate;

	unsigned long min_rate = 0, max_rate = ULONG_MAX;

	unsigned int i;

	int err;

	/* select minimum and maximum rates among the requested rates */

	for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {

		if (i == type) {

			min_rate = max(new_min_rate, min_rate);

			max_rate = min(new_max_rate, max_rate);

		} else {

			min_rate = max(req->min_rate, min_rate);

			max_rate = min(req->max_rate, max_rate);

		}

	}

	if (min_rate > max_rate) {

		dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",

				    __func__, type, min_rate, max_rate);

		return -ERANGE;

	}

	/*

	 * EMC rate-changes should go via OPP API because it manages voltage

	 * changes.

	 */

	err = dev_pm_opp_set_rate(emc->dev, min_rate);

	if (err)

		return err;

	emc->requested_rate[type].min_rate = new_min_rate;

	emc->requested_rate[type].max_rate = new_max_rate;

	return 0;

}

static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,

			    enum emc_rate_request_type type)

{

	struct emc_rate_request *req = &emc->requested_rate[type];

	int ret;

	mutex_lock(&emc->rate_lock);

	ret = emc_request_rate(emc, rate, req->max_rate, type);

	mutex_unlock(&emc->rate_lock);

	return ret;

}

static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,

			    enum emc_rate_request_type type)

{

	struct emc_rate_request *req = &emc->requested_rate[type];

	int ret;

	mutex_lock(&emc->rate_lock);

	ret = emc_request_rate(emc, req->min_rate, rate, type);

	mutex_unlock(&emc->rate_lock);

	return ret;

}

/*

 * debugfs interface

 *

	if (!tegra_emc_validate_rate(emc, rate))

		return -EINVAL;

	err = clk_set_min_rate(emc->clk, rate);

	err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);

	if (err < 0)

		return err;

	if (!tegra_emc_validate_rate(emc, rate))

		return -EINVAL;

	err = clk_set_max_rate(emc->clk, rate);

	err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);

	if (err < 0)

		return err;

			    emc, &tegra_emc_debug_max_rate_fops);

}

static inline struct tegra_emc *

to_tegra_emc_provider(struct icc_provider *provider)

{

	return container_of(provider, struct tegra_emc, provider);

}

static struct icc_node_data *

emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)

{

	struct icc_provider *provider = data;

	struct icc_node_data *ndata;

	struct icc_node *node;

	/* External Memory is the only possible ICC route */

	list_for_each_entry(node, &provider->nodes, node_list) {

		if (node->id != TEGRA_ICC_EMEM)

			continue;

		ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);

		if (!ndata)

			return ERR_PTR(-ENOMEM);

		/*

		 * SRC and DST nodes should have matching TAG in order to have

		 * it set by default for a requested path.

		 */

		ndata->tag = TEGRA_MC_ICC_TAG_ISO;

		ndata->node = node;

		return ndata;

	}

	return ERR_PTR(-EPROBE_DEFER);

}

static int emc_icc_set(struct icc_node *src, struct icc_node *dst)

{

	struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);

	unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);

	unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);

	unsigned long long rate = max(avg_bw, peak_bw);

	const unsigned int dram_data_bus_width_bytes = 4;

	const unsigned int ddr = 2;

	int err;

	/*

	 * Tegra30 EMC runs on a clock rate of SDRAM bus.  This means that

	 * EMC clock rate is twice smaller than the peak data rate because

	 * data is sampled on both EMC clock edges.

	 */

	do_div(rate, ddr * dram_data_bus_width_bytes);

	rate = min_t(u64, rate, U32_MAX);

	err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);

	if (err)

		return err;

	return 0;

}

static int tegra_emc_interconnect_init(struct tegra_emc *emc)

{

	const struct tegra_mc_soc *soc = emc->mc->soc;

	struct icc_node *node;

	int err;

	emc->provider.dev = emc->dev;

	emc->provider.set = emc_icc_set;

	emc->provider.data = &emc->provider;

	emc->provider.aggregate = soc->icc_ops->aggregate;

	emc->provider.xlate_extended = emc_of_icc_xlate_extended;

	err = icc_provider_add(&emc->provider);

	if (err)

		goto err_msg;

	/* create External Memory Controller node */

	node = icc_node_create(TEGRA_ICC_EMC);

	if (IS_ERR(node)) {

		err = PTR_ERR(node);

		goto del_provider;

	}

	node->name = "External Memory Controller";

	icc_node_add(node, &emc->provider);

	/* link External Memory Controller to External Memory (DRAM) */

	err = icc_link_create(node, TEGRA_ICC_EMEM);

	if (err)

		goto remove_nodes;

	/* create External Memory node */

	node = icc_node_create(TEGRA_ICC_EMEM);

	if (IS_ERR(node)) {

		err = PTR_ERR(node);

		goto remove_nodes;

	}

	node->name = "External Memory (DRAM)";

	icc_node_add(node, &emc->provider);

	return 0;

remove_nodes:

	icc_nodes_remove(&emc->provider);

del_provider:

	icc_provider_del(&emc->provider);

err_msg:

	dev_err(emc->dev, "failed to initialize ICC: %d\n", err);

	return err;

}

static int tegra_emc_opp_table_init(struct tegra_emc *emc)

{

	u32 hw_version = BIT(tegra_sku_info.soc_speedo_id);

	struct opp_table *clk_opp_table, *hw_opp_table;

	int err;

	clk_opp_table = dev_pm_opp_set_clkname(emc->dev, NULL);

	err = PTR_ERR_OR_ZERO(clk_opp_table);

	if (err) {

		dev_err(emc->dev, "failed to set OPP clk: %d\n", err);

		return err;

	}

	hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);

	err = PTR_ERR_OR_ZERO(hw_opp_table);

	if (err) {

		dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);

		goto put_clk_table;

	}

	err = dev_pm_opp_of_add_table(emc->dev);

	if (err) {

		if (err == -ENODEV)

			dev_err(emc->dev, "OPP table not found, please update your device tree\n");

		else

			dev_err(emc->dev, "failed to add OPP table: %d\n", err);

		goto put_hw_table;

	}

	dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",

		 hw_version, clk_get_rate(emc->clk) / 1000000);

	/* first dummy rate-set initializes voltage state */

	err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));

	if (err) {

		dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err);

		goto remove_table;

	}

	return 0;

remove_table:

	dev_pm_opp_of_remove_table(emc->dev);

put_hw_table:

	dev_pm_opp_put_supported_hw(hw_opp_table);

put_clk_table:

	dev_pm_opp_put_clkname(clk_opp_table);

	return err;

}

static void devm_tegra_emc_unset_callback(void *data)

{

	tegra20_clk_set_emc_round_callback(NULL, NULL);

}

static void devm_tegra_emc_unreg_clk_notifier(void *data)

{

	struct tegra_emc *emc = data;

	clk_notifier_unregister(emc->clk, &emc->clk_nb);

}

static int tegra_emc_init_clk(struct tegra_emc *emc)

{

	int err;

	tegra20_clk_set_emc_round_callback(emc_round_rate, emc);

	err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback,

				       NULL);

	if (err)

		return err;

	emc->clk = devm_clk_get(emc->dev, NULL);

	if (IS_ERR(emc->clk)) {

		dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk);

		return PTR_ERR(emc->clk);

	}

	err = clk_notifier_register(emc->clk, &emc->clk_nb);

	if (err) {

		dev_err(emc->dev, "failed to register clk notifier: %d\n", err);

		return err;

	}

	err = devm_add_action_or_reset(emc->dev,

				       devm_tegra_emc_unreg_clk_notifier, emc);

	if (err)

		return err;

	return 0;

}

static int tegra_emc_probe(struct platform_device *pdev)

{

	struct device_node *np;

	if (IS_ERR(emc->mc))

		return PTR_ERR(emc->mc);

	mutex_init(&emc->rate_lock);

	emc->clk_nb.notifier_call = emc_clk_change_notify;

	emc->dev = &pdev->dev;

		return err;

	}

	tegra20_clk_set_emc_round_callback(emc_round_rate, emc);

	emc->clk = devm_clk_get(&pdev->dev, "emc");

	if (IS_ERR(emc->clk)) {

		err = PTR_ERR(emc->clk);

		dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);

		goto unset_cb;

	}

	err = tegra_emc_init_clk(emc);

	if (err)

		return err;

	err = clk_notifier_register(emc->clk, &emc->clk_nb);

	if (err) {

		dev_err(&pdev->dev, "failed to register clk notifier: %d\n",

			err);

		goto unset_cb;

	}

	err = tegra_emc_opp_table_init(emc);

	if (err)

		return err;

	platform_set_drvdata(pdev, emc);

	tegra_emc_rate_requests_init(emc);

	tegra_emc_debugfs_init(emc);

	tegra_emc_interconnect_init(emc);

	/*

	 * Don't allow the kernel module to be unloaded. Unloading adds some

	try_module_get(THIS_MODULE);

	return 0;

unset_cb:

	tegra20_clk_set_emc_round_callback(NULL, NULL);

	return err;

}

static int tegra_emc_suspend(struct device *dev)

		.of_match_table = tegra_emc_of_match,

		.pm = &tegra_emc_pm_ops,

		.suppress_bind_attrs = true,

		.sync_state = icc_sync_state,

	},

};

module_platform_driver(tegra_emc_driver);

 */

#include <linux/of.h>

#include <linux/mm.h>

#include <linux/of_device.h>

#include <linux/slab.h>

#include <dt-bindings/memory/tegra30-mc.h>

	TEGRA30_MC_RESET(VI,       0x200, 0x204, 17),

};

static void tegra30_mc_tune_client_latency(struct tegra_mc *mc,

					   const struct tegra_mc_client *client,

					   unsigned int bandwidth_mbytes_sec)

{

	u32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div;

	const struct tegra_mc_la *la = &client->la;

	unsigned int fifo_size = client->fifo_size;

	u32 arb_nsec, la_ticks, value;

	/* see 18.4.1 Client Configuration in Tegra3 TRM v03p */

	if (bandwidth_mbytes_sec)

		arb_nsec = fifo_size * NSEC_PER_USEC / bandwidth_mbytes_sec;

	else

		arb_nsec = U32_MAX;

	/*

	 * Latency allowness should be set with consideration for the module's

	 * latency tolerance and internal buffering capabilities.

	 *

	 * Display memory clients use isochronous transfers and have very low

	 * tolerance to a belated transfers. Hence we need to compensate the

	 * memory arbitration imperfection for them in order to prevent FIFO

	 * underflow condition when memory bus is busy.

	 *

	 * VI clients also need a stronger compensation.

	 */

	switch (client->swgroup) {

	case TEGRA_SWGROUP_MPCORE:

	case TEGRA_SWGROUP_PTC:

		/*

		 * We always want lower latency for these clients, hence

		 * don't touch them.

		 */

		return;

	case TEGRA_SWGROUP_DC:

	case TEGRA_SWGROUP_DCB:

		arb_tolerance_compensation_nsec = 1050;

		arb_tolerance_compensation_div = 2;

		break;

	case TEGRA_SWGROUP_VI:

		arb_tolerance_compensation_nsec = 1050;

		arb_tolerance_compensation_div = 1;

		break;

	default:

		arb_tolerance_compensation_nsec = 150;

		arb_tolerance_compensation_div = 1;

		break;

	}

	if (arb_nsec > arb_tolerance_compensation_nsec)

		arb_nsec -= arb_tolerance_compensation_nsec;

	else

		arb_nsec = 0;

	arb_nsec /= arb_tolerance_compensation_div;

	/*

	 * Latency allowance is a number of ticks a request from a particular

	 * client may wait in the EMEM arbiter before it becomes a high-priority

	 * request.

	 */

	la_ticks = arb_nsec / mc->tick;

	la_ticks = min(la_ticks, la->mask);

	value = mc_readl(mc, la->reg);

	value &= ~(la->mask << la->shift);

	value |= la_ticks << la->shift;

	mc_writel(mc, value, la->reg);

}

static int tegra30_mc_icc_set(struct icc_node *src, struct icc_node *dst)

{

	struct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider);

	const struct tegra_mc_client *client = &mc->soc->clients[src->id];

	u64 peak_bandwidth = icc_units_to_bps(src->peak_bw);

	/*

	 * Skip pre-initialization that is done by icc_node_add(), which sets

	 * bandwidth to maximum for all clients before drivers are loaded.

	 *

	 * This doesn't make sense for us because we don't have drivers for all

	 * clients and it's okay to keep configuration left from bootloader

	 * during boot, at least for today.

	 */

	if (src == dst)

		return 0;

	/* convert bytes/sec to megabytes/sec */

	do_div(peak_bandwidth, 1000000);

	tegra30_mc_tune_client_latency(mc, client, peak_bandwidth);

	return 0;

}

static int tegra30_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,

				   u32 peak_bw, u32 *agg_avg, u32 *agg_peak)

{

	/*

	 * ISO clients need to reserve extra bandwidth up-front because

	 * there could be high bandwidth pressure during initial filling

	 * of the client's FIFO buffers.  Secondly, we need to take into

	 * account impurities of the memory subsystem.

	 */

	if (tag & TEGRA_MC_ICC_TAG_ISO)

		peak_bw = tegra_mc_scale_percents(peak_bw, 400);

	*agg_avg += avg_bw;

	*agg_peak = max(*agg_peak, peak_bw);

	return 0;

}

static struct icc_node_data *

tegra30_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)

{

	struct tegra_mc *mc = icc_provider_to_tegra_mc(data);

	const struct tegra_mc_client *client;

	unsigned int i, idx = spec->args[0];

	struct icc_node_data *ndata;

	struct icc_node *node;

	list_for_each_entry(node, &mc->provider.nodes, node_list) {

		if (node->id != idx)

			continue;

		ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);

		if (!ndata)

			return ERR_PTR(-ENOMEM);