Commit 625326ea authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: Remove PNX833x alias NXP_STB22x 



Remove another unused MIPS platform.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 725ac66e

arch/mips/Kbuild.platforms

+0 −1
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ platform-$(CONFIG_MIPS_MALTA) += mti-malta/ 
platform-$(CONFIG_NLM_COMMON)		+= netlogic/

platform-$(CONFIG_PIC32MZDA)		+= pic32/

platform-$(CONFIG_MACH_PISTACHIO)	+= pistachio/

platform-$(CONFIG_SOC_PNX833X)		+= pnx833x/

platform-$(CONFIG_RALINK)		+= ralink/

platform-$(CONFIG_MIKROTIK_RB532)	+= rb532/

platform-$(CONFIG_SGI_IP22)		+= sgi-ip22/

arch/mips/Kconfig

+0 −30
Original line number Diff line number Diff line
@@ -589,19 +589,6 @@ config MACH_VR41XX 
	select SYS_SUPPORTS_MIPS16

	select GPIOLIB



config NXP_STB220

	bool "NXP STB220 board"

	select SOC_PNX833X

	help

	  Support for NXP Semiconductors STB220 Development Board.



config NXP_STB225

	bool "NXP 225 board"

	select SOC_PNX833X

	select SOC_PNX8335

	help

	  Support for NXP Semiconductors STB225 Development Board.



config RALINK

	bool "Ralink based machines"

	select CEVT_R4K
@@ -1266,23 +1253,6 @@ config PCI_XTALK_BRIDGE 
config NO_EXCEPT_FILL

	bool



config SOC_PNX833X

	bool

	select CEVT_R4K

	select CSRC_R4K

	select IRQ_MIPS_CPU

	select DMA_NONCOHERENT

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_MIPS16

	select CPU_MIPSR2_IRQ_VI



config SOC_PNX8335

	bool

	select SOC_PNX833X



config MIPS_SPRAM

	bool

arch/mips/configs/pnx8335_stb225_defconfig

deleted100644 → 0
+0 −77
Original line number Diff line number Diff line 
# CONFIG_LOCALVERSION_AUTO is not set

# CONFIG_SWAP is not set

CONFIG_SYSVIPC=y

CONFIG_NO_HZ=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_PREEMPT_VOLUNTARY=y

CONFIG_LOG_BUF_SHIFT=14

CONFIG_EXPERT=y

CONFIG_SLAB=y

CONFIG_NXP_STB225=y

CONFIG_CPU_LITTLE_ENDIAN=y

CONFIG_HZ_128=y

# CONFIG_SECCOMP is not set

CONFIG_MODULES=y

CONFIG_MODULE_UNLOAD=y

# CONFIG_BLK_DEV_BSG is not set

CONFIG_NET=y

CONFIG_PACKET=y

CONFIG_UNIX=y

CONFIG_INET=y

CONFIG_IP_MULTICAST=y

CONFIG_IP_PNP=y

CONFIG_IP_PNP_DHCP=y

CONFIG_INET_AH=y

# CONFIG_IPV6 is not set

CONFIG_MTD=y

CONFIG_MTD_CMDLINE_PARTS=y

CONFIG_MTD_BLOCK=y

CONFIG_MTD_CFI=y

CONFIG_MTD_CFI_ADV_OPTIONS=y

CONFIG_MTD_CFI_LE_BYTE_SWAP=y

CONFIG_MTD_CFI_GEOMETRY=y

CONFIG_MTD_CFI_AMDSTD=y

CONFIG_MTD_PHYSMAP=y

CONFIG_BLK_DEV_LOOP=y

CONFIG_BLK_DEV_SD=y

# CONFIG_SCSI_LOWLEVEL is not set

CONFIG_ATA=y

CONFIG_NETDEVICES=y

CONFIG_INPUT_EVDEV=m

CONFIG_INPUT_EVBUG=m

# CONFIG_INPUT_KEYBOARD is not set

# CONFIG_INPUT_MOUSE is not set

# CONFIG_VT_CONSOLE is not set

# CONFIG_LEGACY_PTYS is not set

CONFIG_SERIAL_PNX8XXX=y

CONFIG_SERIAL_PNX8XXX_CONSOLE=y

CONFIG_HW_RANDOM=y

CONFIG_I2C=y

CONFIG_I2C_CHARDEV=y

# CONFIG_HWMON is not set

CONFIG_FB=y

# CONFIG_VGA_CONSOLE is not set

CONFIG_SOUND=m

CONFIG_SND=m

CONFIG_SND_VERBOSE_PRINTK=y

CONFIG_SND_DEBUG=y

CONFIG_SND_SEQUENCER=m

CONFIG_EXT2_FS=m

# CONFIG_DNOTIFY is not set

CONFIG_MSDOS_FS=m

CONFIG_VFAT_FS=m

CONFIG_TMPFS=y

CONFIG_JFFS2_FS=y

CONFIG_CRAMFS=y

CONFIG_NFS_FS=y

CONFIG_ROOT_NFS=y

CONFIG_NFSD=m

CONFIG_NFSD_V3=y

CONFIG_NLS=y

CONFIG_NLS_CODEPAGE_437=m

CONFIG_NLS_CODEPAGE_850=m

CONFIG_NLS_CODEPAGE_932=m

CONFIG_NLS_ASCII=m

CONFIG_NLS_ISO8859_1=m

CONFIG_NLS_ISO8859_15=m

CONFIG_NLS_UTF8=m

arch/mips/include/asm/mach-pnx833x/gpio.h

deleted100644 → 0
+0 −159
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 *  gpio.h: GPIO Support for PNX833X.

 *

 *  Copyright 2008 NXP Semiconductors

 *	  Chris Steel <chris.steel@nxp.com>

 *    Daniel Laird <daniel.j.laird@nxp.com>

 */

#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H

#define __ASM_MIPS_MACH_PNX833X_GPIO_H



/* BIG FAT WARNING: races danger!

   No protections exist here. Current users are only early init code,

   when locking is not needed because no concurrency yet exists there,

   and GPIO IRQ dispatcher, which does locking.

   However, if many uses will ever happen, proper locking will be needed

   - including locking between different uses

*/



#include <asm/mach-pnx833x/pnx833x.h>



#define SET_REG_BIT(reg, bit)		do { (reg |= (1 << (bit))); } while (0)

#define CLEAR_REG_BIT(reg, bit)		do { (reg &= ~(1 << (bit))); } while (0)



/* Initialize GPIO to a known state */

static inline void pnx833x_gpio_init(void)

{

	PNX833X_PIO_DIR = 0;

	PNX833X_PIO_DIR2 = 0;

	PNX833X_PIO_SEL = 0;

	PNX833X_PIO_SEL2 = 0;

	PNX833X_PIO_INT_EDGE = 0;

	PNX833X_PIO_INT_HI = 0;

	PNX833X_PIO_INT_LO = 0;



	/* clear any GPIO interrupt requests */

	PNX833X_PIO_INT_CLEAR = 0xffff;

	PNX833X_PIO_INT_CLEAR = 0;

	PNX833X_PIO_INT_ENABLE = 0;

}



/* Select GPIO direction for a pin */

static inline void pnx833x_gpio_select_input(unsigned int pin)

{

	if (pin < 32)

		CLEAR_REG_BIT(PNX833X_PIO_DIR, pin);

	else

		CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31);

}

static inline void pnx833x_gpio_select_output(unsigned int pin)

{

	if (pin < 32)

		SET_REG_BIT(PNX833X_PIO_DIR, pin);

	else

		SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);

}



/* Select GPIO or alternate function for a pin */

static inline void pnx833x_gpio_select_function_io(unsigned int pin)

{

	if (pin < 32)

		CLEAR_REG_BIT(PNX833X_PIO_SEL, pin);

	else

		CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31);

}

static inline void pnx833x_gpio_select_function_alt(unsigned int pin)

{

	if (pin < 32)

		SET_REG_BIT(PNX833X_PIO_SEL, pin);

	else

		SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);

}



/* Read GPIO pin */

static inline int pnx833x_gpio_read(unsigned int pin)

{

	if (pin < 32)

		return (PNX833X_PIO_IN >> pin) & 1;

	else

		return (PNX833X_PIO_IN2 >> (pin & 31)) & 1;

}



/* Write GPIO pin */

static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin)

{

	if (pin < 32) {

		if (val)

			SET_REG_BIT(PNX833X_PIO_OUT, pin);

		else

			CLEAR_REG_BIT(PNX833X_PIO_OUT, pin);

	} else {

		if (val)

			SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);

		else

			CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31);

	}

}



/* Configure GPIO interrupt */

#define GPIO_INT_NONE		0

#define GPIO_INT_LEVEL_LOW	1

#define GPIO_INT_LEVEL_HIGH	2

#define GPIO_INT_EDGE_RISING	3

#define GPIO_INT_EDGE_FALLING	4

#define GPIO_INT_EDGE_BOTH	5

static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin)

{

	switch (when) {

	case GPIO_INT_LEVEL_LOW:

		CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);

		CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);

		SET_REG_BIT(PNX833X_PIO_INT_LO, pin);

		break;

	case GPIO_INT_LEVEL_HIGH:

		CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);

		SET_REG_BIT(PNX833X_PIO_INT_HI, pin);

		CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);

		break;

	case GPIO_INT_EDGE_RISING:

		SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);

		SET_REG_BIT(PNX833X_PIO_INT_HI, pin);

		CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);

		break;

	case GPIO_INT_EDGE_FALLING:

		SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);

		CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);

		SET_REG_BIT(PNX833X_PIO_INT_LO, pin);

		break;

	case GPIO_INT_EDGE_BOTH:

		SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);

		SET_REG_BIT(PNX833X_PIO_INT_HI, pin);

		SET_REG_BIT(PNX833X_PIO_INT_LO, pin);

		break;

	default:

		CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);

		CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);

		CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);

		break;

	}

}



/* Enable/disable GPIO interrupt */

static inline void pnx833x_gpio_enable_irq(unsigned int pin)

{

	SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);

}

static inline void pnx833x_gpio_disable_irq(unsigned int pin)

{

	CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);

}



/* Clear GPIO interrupt request */

static inline void pnx833x_gpio_clear_irq(unsigned int pin)

{

	SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);

	CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);

}



#endif

arch/mips/include/asm/mach-pnx833x/irq-mapping.h

deleted100644 → 0
+0 −112
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */



/*

 *  irq.h: IRQ mappings for PNX833X.

 *

 *  Copyright 2008 NXP Semiconductors

 *	  Chris Steel <chris.steel@nxp.com>

 *    Daniel Laird <daniel.j.laird@nxp.com>

 */



#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H

#define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H

/*

 * The "IRQ numbers" are completely virtual.

 *

 * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.

 * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,

 * numbers 49..64 for (virtual) GPIO interrupts.

 *

 * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,

 * connected to PIC, which uses core hardware interrupt 2, and also

 * a timer interrupt through hardware interrupt 5.

 * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,

 * numbers 65..80 for (virtual) GPIO interrupts.

 *

 */

#include <irq.h>



#define PNX833X_TIMER_IRQ				(MIPS_CPU_IRQ_BASE + 7)



/* Interrupts supported by PIC */

#define PNX833X_PIC_I2C0_INT			(PNX833X_PIC_IRQ_BASE +	 1)

#define PNX833X_PIC_I2C1_INT			(PNX833X_PIC_IRQ_BASE +	 2)

#define PNX833X_PIC_UART0_INT			(PNX833X_PIC_IRQ_BASE +	 3)

#define PNX833X_PIC_UART1_INT			(PNX833X_PIC_IRQ_BASE +	 4)

#define PNX833X_PIC_TS_IN0_DV_INT		(PNX833X_PIC_IRQ_BASE +	 5)

#define PNX833X_PIC_TS_IN0_DMA_INT		(PNX833X_PIC_IRQ_BASE +	 6)

#define PNX833X_PIC_GPIO_INT			(PNX833X_PIC_IRQ_BASE +	 7)

#define PNX833X_PIC_AUDIO_DEC_INT		(PNX833X_PIC_IRQ_BASE +	 8)

#define PNX833X_PIC_VIDEO_DEC_INT		(PNX833X_PIC_IRQ_BASE +	 9)

#define PNX833X_PIC_CONFIG_INT			(PNX833X_PIC_IRQ_BASE + 10)

#define PNX833X_PIC_AOI_INT				(PNX833X_PIC_IRQ_BASE + 11)

#define PNX833X_PIC_SYNC_INT			(PNX833X_PIC_IRQ_BASE + 12)

#define PNX8330_PIC_SPU_INT				(PNX833X_PIC_IRQ_BASE + 13)

#define PNX8335_PIC_SATA_INT			(PNX833X_PIC_IRQ_BASE + 13)

#define PNX833X_PIC_OSD_INT				(PNX833X_PIC_IRQ_BASE + 14)

#define PNX833X_PIC_DISP1_INT			(PNX833X_PIC_IRQ_BASE + 15)

#define PNX833X_PIC_DEINTERLACER_INT	(PNX833X_PIC_IRQ_BASE + 16)

#define PNX833X_PIC_DISPLAY2_INT		(PNX833X_PIC_IRQ_BASE + 17)

#define PNX833X_PIC_VC_INT				(PNX833X_PIC_IRQ_BASE + 18)

#define PNX833X_PIC_SC_INT				(PNX833X_PIC_IRQ_BASE + 19)

#define PNX833X_PIC_IDE_INT				(PNX833X_PIC_IRQ_BASE + 20)

#define PNX833X_PIC_IDE_DMA_INT			(PNX833X_PIC_IRQ_BASE + 21)

#define PNX833X_PIC_TS_IN1_DV_INT		(PNX833X_PIC_IRQ_BASE + 22)

#define PNX833X_PIC_TS_IN1_DMA_INT		(PNX833X_PIC_IRQ_BASE + 23)

#define PNX833X_PIC_SGDX_DMA_INT		(PNX833X_PIC_IRQ_BASE + 24)

#define PNX833X_PIC_TS_OUT_INT			(PNX833X_PIC_IRQ_BASE + 25)

#define PNX833X_PIC_IR_INT				(PNX833X_PIC_IRQ_BASE + 26)

#define PNX833X_PIC_VMSP1_INT			(PNX833X_PIC_IRQ_BASE + 27)

#define PNX833X_PIC_VMSP2_INT			(PNX833X_PIC_IRQ_BASE + 28)

#define PNX833X_PIC_PIBC_INT			(PNX833X_PIC_IRQ_BASE + 29)

#define PNX833X_PIC_TS_IN0_TRD_INT		(PNX833X_PIC_IRQ_BASE + 30)

#define PNX833X_PIC_SGDX_TPD_INT		(PNX833X_PIC_IRQ_BASE + 31)

#define PNX833X_PIC_USB_INT				(PNX833X_PIC_IRQ_BASE + 32)

#define PNX833X_PIC_TS_IN1_TRD_INT		(PNX833X_PIC_IRQ_BASE + 33)

#define PNX833X_PIC_CLOCK_INT			(PNX833X_PIC_IRQ_BASE + 34)

#define PNX833X_PIC_SGDX_PARSER_INT		(PNX833X_PIC_IRQ_BASE + 35)

#define PNX833X_PIC_VMSP_DMA_INT		(PNX833X_PIC_IRQ_BASE + 36)



#if defined(CONFIG_SOC_PNX8335)

#define PNX8335_PIC_MIU_INT					(PNX833X_PIC_IRQ_BASE + 37)

#define PNX8335_PIC_AVCHIP_IRQ_INT			(PNX833X_PIC_IRQ_BASE + 38)

#define PNX8335_PIC_SYNC_HD_INT				(PNX833X_PIC_IRQ_BASE + 39)

#define PNX8335_PIC_DISP_HD_INT				(PNX833X_PIC_IRQ_BASE + 40)

#define PNX8335_PIC_DISP_SCALER_INT			(PNX833X_PIC_IRQ_BASE + 41)

#define PNX8335_PIC_OSD_HD1_INT				(PNX833X_PIC_IRQ_BASE + 42)

#define PNX8335_PIC_DTL_WRITER_Y_INT		(PNX833X_PIC_IRQ_BASE + 43)

#define PNX8335_PIC_DTL_WRITER_C_INT		(PNX833X_PIC_IRQ_BASE + 44)

#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT	(PNX833X_PIC_IRQ_BASE + 45)

#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT	(PNX833X_PIC_IRQ_BASE + 46)

#define PNX8335_PIC_DENC_TTX_INT			(PNX833X_PIC_IRQ_BASE + 47)

#define PNX8335_PIC_MMI_SIF0_INT			(PNX833X_PIC_IRQ_BASE + 48)

#define PNX8335_PIC_MMI_SIF1_INT			(PNX833X_PIC_IRQ_BASE + 49)

#define PNX8335_PIC_MMI_CDMMU_INT			(PNX833X_PIC_IRQ_BASE + 50)

#define PNX8335_PIC_PIBCS_INT				(PNX833X_PIC_IRQ_BASE + 51)

#define PNX8335_PIC_ETHERNET_INT			(PNX833X_PIC_IRQ_BASE + 52)

#define PNX8335_PIC_VMSP1_0_INT				(PNX833X_PIC_IRQ_BASE + 53)

#define PNX8335_PIC_VMSP1_1_INT				(PNX833X_PIC_IRQ_BASE + 54)

#define PNX8335_PIC_VMSP1_DMA_INT			(PNX833X_PIC_IRQ_BASE + 55)

#define PNX8335_PIC_TDGR_DE_INT				(PNX833X_PIC_IRQ_BASE + 56)

#define PNX8335_PIC_IR1_IRQ_INT				(PNX833X_PIC_IRQ_BASE + 57)

#endif



/* GPIO interrupts */

#define PNX833X_GPIO_0_INT			(PNX833X_GPIO_IRQ_BASE +  0)

#define PNX833X_GPIO_1_INT			(PNX833X_GPIO_IRQ_BASE +  1)

#define PNX833X_GPIO_2_INT			(PNX833X_GPIO_IRQ_BASE +  2)

#define PNX833X_GPIO_3_INT			(PNX833X_GPIO_IRQ_BASE +  3)

#define PNX833X_GPIO_4_INT			(PNX833X_GPIO_IRQ_BASE +  4)

#define PNX833X_GPIO_5_INT			(PNX833X_GPIO_IRQ_BASE +  5)

#define PNX833X_GPIO_6_INT			(PNX833X_GPIO_IRQ_BASE +  6)

#define PNX833X_GPIO_7_INT			(PNX833X_GPIO_IRQ_BASE +  7)

#define PNX833X_GPIO_8_INT			(PNX833X_GPIO_IRQ_BASE +  8)

#define PNX833X_GPIO_9_INT			(PNX833X_GPIO_IRQ_BASE +  9)

#define PNX833X_GPIO_10_INT			(PNX833X_GPIO_IRQ_BASE + 10)

#define PNX833X_GPIO_11_INT			(PNX833X_GPIO_IRQ_BASE + 11)

#define PNX833X_GPIO_12_INT			(PNX833X_GPIO_IRQ_BASE + 12)

#define PNX833X_GPIO_13_INT			(PNX833X_GPIO_IRQ_BASE + 13)

#define PNX833X_GPIO_14_INT			(PNX833X_GPIO_IRQ_BASE + 14)

#define PNX833X_GPIO_15_INT			(PNX833X_GPIO_IRQ_BASE + 15)



#endif

CRA Git | Maintained and supported by SUSTech CRA and CCSE