MIPS: Paravirt: remove remaining pieces of paravirt (725ac66e) · Commits · 戴 / test

arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h

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		/*
		* This file is subject to the terms and conditions of the GNU General Public
		* License. See the file "COPYING" in the main directory of this archive
		* for more details.
		*
		* Copyright (C) 2013 Cavium, Inc.
		*/
		#ifndef __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H
		#define __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H

		#define cpu_has_4kex 1
		#define cpu_has_3k_cache 0
		#define cpu_has_tx39_cache 0
		#define cpu_has_counter 1
		#define cpu_has_llsc 1
		/*
		* We Disable LL/SC on non SMP systems as it is faster to disable
		* interrupts for atomic access than a LL/SC.
		*/
		#ifdef CONFIG_SMP
		# define kernel_uses_llsc 1
		#else
		# define kernel_uses_llsc 0
		#endif

		#ifdef CONFIG_CPU_CAVIUM_OCTEON
		#define cpu_dcache_line_size() 128
		#define cpu_icache_line_size() 128
		#define cpu_has_octeon_cache 1
		#define cpu_has_4k_cache 0
		#else
		#define cpu_has_4k_cache 1
		#endif

		#endif /* __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H */

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		/*
		* This file is subject to the terms and conditions of the GNU General Public
		* License. See the file "COPYING" in the main directory of this archive
		* for more details.
		*
		* Copyright (C) 2013 Cavium, Inc.
		*/
		#ifndef __ASM_MACH_PARAVIRT_IRQ_H__
		#define __ASM_MACH_PARAVIRT_IRQ_H__

		#define NR_IRQS 64
		#define MIPS_CPU_IRQ_BASE 1

		#define MIPS_IRQ_PCIA (MIPS_CPU_IRQ_BASE + 8)

		#define MIPS_IRQ_MBOX0 (MIPS_CPU_IRQ_BASE + 32)
		#define MIPS_IRQ_MBOX1 (MIPS_CPU_IRQ_BASE + 33)

		#endif /* __ASM_MACH_PARAVIRT_IRQ_H__ */

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		/*
		* This file is subject to the terms and conditions of the GNU General Public
		* License. See the file "COPYING" in the main directory of this archive
		* for more details.
		*
		* Copyright (C) 2013 Cavium, Inc
		*/
		#ifndef __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H
		#define __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H

		#define CP0_EBASE $15, 1

		.macro kernel_entry_setup
		#ifdef CONFIG_SMP
		mfc0 t0, CP0_EBASE
		andi t0, t0, 0x3ff # CPUNum
		beqz t0, 1f
		# CPUs other than zero goto smp_bootstrap
		j smp_bootstrap
		#endif /* CONFIG_SMP */

		1:
		.endm

		/*
		* Do SMP slave processor setup necessary before we can safely execute
		* C code.
		*/
		.macro smp_slave_setup
		mfc0 t0, CP0_EBASE
		andi t0, t0, 0x3ff # CPUNum
		slti t1, t0, NR_CPUS
		bnez t1, 1f
		2:
		di
		wait
		b 2b # Unknown CPU, loop forever.
		1:
		PTR_LA t1, paravirt_smp_sp
		PTR_SLL t0, PTR_SCALESHIFT
		PTR_ADDU t1, t1, t0
		3:
		PTR_L sp, 0(t1)
		beqz sp, 3b # Spin until told to proceed.

		PTR_LA t1, paravirt_smp_gp
		PTR_ADDU t1, t1, t0
		sync
		PTR_L gp, 0(t1)
		.endm

		#endif /* __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H */