Commit 62531104 authored by Dien Pham's avatar Dien Pham Committed by Simon Horman
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arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices 



This patch adds OPPs table for CA57{0,1} cpu devices

Signed-off-by: default avatarDien Pham <dien.pham.ry@renesas.com>
Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: default avatarYoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: default avatarSimon Horman <horms+renesas@verge.net.au>
[simon: do not give nodes unit names as they have no bus addresses]
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 83ff28c7

arch/arm64/boot/dts/renesas/r8a77965.dtsi

+44 −0
Original line number Diff line number Diff line
@@ -60,6 +60,46 @@ 
		clock-frequency = <0>;

	};



	cluster0_opp: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp-500000000 {

			opp-hz = /bits/ 64 <500000000>;

			opp-microvolt = <830000>;

			clock-latency-ns = <300000>;

		};

		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <830000>;

			clock-latency-ns = <300000>;

		};

		opp-1500000000 {

			opp-hz = /bits/ 64 <1500000000>;

			opp-microvolt = <830000>;

			clock-latency-ns = <300000>;

			opp-suspend;

		};

		opp-1600000000 {

			opp-hz = /bits/ 64 <1600000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <300000>;

			turbo-mode;

		};

		opp-1700000000 {

			opp-hz = /bits/ 64 <1700000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <300000>;

			turbo-mode;

		};

		opp-1800000000 {

			opp-hz = /bits/ 64 <1800000000>;

			opp-microvolt = <960000>;

			clock-latency-ns = <300000>;

			turbo-mode;

		};

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -71,6 +111,8 @@ 
			power-domains = <&sysc R8A77965_PD_CA57_CPU0>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A77965_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

		};



		a57_1: cpu@1 {
@@ -80,6 +122,8 @@ 
			power-domains = <&sysc R8A77965_PD_CA57_CPU1>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A77965_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

		};



		L2_CA57: cache-controller-0 {

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