Commit 60107c77 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'samsung-dt-5.5' of... 

Merge tag 'samsung-dt-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Samsung DTS ARM changes for v5.5

1. Add ARM architected timers on Exynos5 for KVM-based virtualization,
2. Extend chip identification needed for future Adaptive Supply Voltage,
3. Add audio support to Arndale board,
4. Fix init order of clock providers on s3c64xx,
5. A lot of cleanups and adjustments of DTS with DT schema.

* tag 'samsung-dt-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: s3c64xx: Fix init order of clock providers
  ARM: dts: exynos: Rename SysRAM node to "sram"
  ARM: dts: exynos: Rename power domain nodes to "power-domain" in Exynos4
  ARM: dts: exynos: Add audio support (WM1811 CODEC boards) to Arndale board
  ARM: dts: exynos: Use defines for MCT interrupt GIC SPI/PPI specifier
  ARM: dts: exynos: Remove MCT subnode for interrupt map on Exynos54xx
  ARM: dts: exynos: Remove MCT subnode for interrupt map on Exynos5250
  ARM: dts: exynos: Remove MCT subnode for interrupt map on Exynos4412
  ARM: dts: exynos: Remove MCT subnode for interrupt map on Exynos4210
  ARM: dts: exynos: Rename Multi Core Timer node to "timer"
  ARM: dts: exynos: Split phandle in dmas property
  ARM: dts: exynos: Remove obsolete IRQ lines on Exynos3250
  ARM: dts: exynos: Add samsung,asv-bin property to Odroid XU3 Lite
  ARM: dts: exynos: Add "syscon" compatible string to chipid node on Exynos5
  ARM: dts: exynos: Add support ARM architected timers on Exynos5

Link: https://lore.kernel.org/r/20191021180453.29455-4-krzk@kernel.org


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents ee1d28a4 d60d0cff

arch/arm/boot/dts/exynos3250.dtsi

+5 −8
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ 
		#size-cells = <1>;

		ranges;



		sysram@2020000 {

		sram@2020000 {

			compatible = "mmio-sram";

			reg = <0x02020000 0x40000>;

			#address-cells = <1>;
@@ -265,7 +265,7 @@ 
					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

		};



		mct@10050000 {

		timer@10050000 {

			compatible = "samsung,exynos4210-mct";

			reg = <0x10050000 0x800>;

			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
@@ -314,8 +314,7 @@ 
		sysmmu_jpeg: sysmmu@11a60000 {

			compatible = "samsung,exynos-sysmmu";

			reg = <0x11a60000 0x1000>;

			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "sysmmu", "master";

			clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;

			power-domains = <&pd_cam>;
@@ -355,8 +354,7 @@ 
		sysmmu_fimd0: sysmmu@11e20000 {

			compatible = "samsung,exynos-sysmmu";

			reg = <0x11e20000 0x1000>;

			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "sysmmu", "master";

			clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;

			power-domains = <&pd_lcd0>;
@@ -507,8 +505,7 @@ 
		sysmmu_mfc: sysmmu@13620000 {

			compatible = "samsung,exynos-sysmmu";

			reg = <0x13620000 0x1000>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "sysmmu", "master";

			clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;

			power-domains = <&pd_mfc>;

arch/arm/boot/dts/exynos4.dtsi

+7 −7
Original line number Diff line number Diff line
@@ -111,28 +111,28 @@ 
			syscon = <&pmu_system_controller>;

		};



		pd_mfc: mfc-power-domain@10023c40 {

		pd_mfc: power-domain@10023c40 {

			compatible = "samsung,exynos4210-pd";

			reg = <0x10023C40 0x20>;

			#power-domain-cells = <0>;

			label = "MFC";

		};



		pd_g3d: g3d-power-domain@10023c60 {

		pd_g3d: power-domain@10023c60 {

			compatible = "samsung,exynos4210-pd";

			reg = <0x10023C60 0x20>;

			#power-domain-cells = <0>;

			label = "G3D";

		};



		pd_lcd0: lcd0-power-domain@10023c80 {

		pd_lcd0: power-domain@10023c80 {

			compatible = "samsung,exynos4210-pd";

			reg = <0x10023C80 0x20>;

			#power-domain-cells = <0>;

			label = "LCD0";

		};



		pd_tv: tv-power-domain@10023c20 {

		pd_tv: power-domain@10023c20 {

			compatible = "samsung,exynos4210-pd";

			reg = <0x10023C20 0x20>;

			#power-domain-cells = <0>;
@@ -140,21 +140,21 @@ 
			label = "TV";

		};



		pd_cam: cam-power-domain@10023c00 {

		pd_cam: power-domain@10023c00 {

			compatible = "samsung,exynos4210-pd";

			reg = <0x10023C00 0x20>;

			#power-domain-cells = <0>;

			label = "CAM";

		};



		pd_gps: gps-power-domain@10023ce0 {

		pd_gps: power-domain@10023ce0 {

			compatible = "samsung,exynos4210-pd";

			reg = <0x10023CE0 0x20>;

			#power-domain-cells = <0>;

			label = "GPS";

		};



		pd_gps_alive: gps-alive-power-domain@10023d00 {

		pd_gps_alive: power-domain@10023d00 {

			compatible = "samsung,exynos4210-pd";

			reg = <0x10023D00 0x20>;

			#power-domain-cells = <0>;

arch/arm/boot/dts/exynos4210.dtsi

+9 −18
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ 
	};



	soc: soc {

		sysram: sysram@2020000 {

		sysram: sram@2020000 {

			compatible = "mmio-sram";

			reg = <0x02020000 0x20000>;

			#address-cells = <1>;
@@ -90,7 +90,7 @@ 
			};

		};



		pd_lcd1: lcd1-power-domain@10023ca0 {

		pd_lcd1: power-domain@10023ca0 {

			compatible = "samsung,exynos4210-pd";

			reg = <0x10023CA0 0x20>;

			#power-domain-cells = <0>;
@@ -106,26 +106,17 @@ 
			arm,data-latency = <2 2 1>;

		};



		mct: mct@10050000 {

		mct: timer@10050000 {

			compatible = "samsung,exynos4210-mct";

			reg = <0x10050000 0x800>;

			interrupt-parent = <&mct_map>;

			interrupts = <0>, <1>, <2>, <3>, <4>, <5>;

			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;

			clock-names = "fin_pll", "mct";



			mct_map: mct-map {

				#interrupt-cells = <1>;

				#address-cells = <0>;

				#size-cells = <0>;

				interrupt-map =

					<0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,

					<1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,

					<2 &combiner 12 6>,

					<3 &combiner 12 7>,

					<4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,

					<5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;

			};

			interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,

					      <&combiner 12 6>,

					      <&combiner 12 7>,

					      <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

		};



		watchdog: watchdog@10060000 {

arch/arm/boot/dts/exynos4412.dtsi

+8 −17
Original line number Diff line number Diff line
@@ -188,7 +188,7 @@ 
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

		};



		sysram@2020000 {

		sram@2020000 {

			compatible = "mmio-sram";

			reg = <0x02020000 0x40000>;

			#address-cells = <1>;
@@ -206,7 +206,7 @@ 
			};

		};



		pd_isp: isp-power-domain@10023ca0 {

		pd_isp: power-domain@10023ca0 {

			compatible = "samsung,exynos4210-pd";

			reg = <0x10023CA0 0x20>;

			#power-domain-cells = <0>;
@@ -243,25 +243,16 @@ 
			clock-names = "aclk200", "aclk400_mcuisp";

		};



		mct@10050000 {

		timer@10050000 {

			compatible = "samsung,exynos4412-mct";

			reg = <0x10050000 0x800>;

			interrupt-parent = <&mct_map>;

			interrupts = <0>, <1>, <2>, <3>, <4>;

			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;

			clock-names = "fin_pll", "mct";



			mct_map: mct-map {

				#interrupt-cells = <1>;

				#address-cells = <0>;

				#size-cells = <0>;

				interrupt-map =

					<0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,

					<1 &combiner 12 5>,

					<2 &combiner 12 6>,

					<3 &combiner 12 7>,

					<4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;

			};

			interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

					      <&combiner 12 5>,

					      <&combiner 12 6>,

					      <&combiner 12 7>,

					      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;

		};



		watchdog: watchdog@10060000 {

arch/arm/boot/dts/exynos5.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -35,8 +35,8 @@ 
		#size-cells = <1>;

		ranges;



		chipid@10000000 {

			compatible = "samsung,exynos4210-chipid";

		chipid: chipid@10000000 {

			compatible = "samsung,exynos4210-chipid", "syscon";

			reg = <0x10000000 0x100>;

		};

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