Commit 5f56888f authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-ingenic', 'clk-at91', 'clk-kconfig', 'clk-imx',...

Merge branches 'clk-ingenic', 'clk-at91', 'clk-kconfig', 'clk-imx', 'clk-qcom', 'clk-prima2' and 'clk-bcm' into clk-next

 - Support qcom SM8150/SM8250 video and display clks
 - Change how qcom's display port clks work

* clk-ingenic:
  clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
  clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
  clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
  clk: ingenic: Use readl_poll_timeout instead of custom loop
  clk: ingenic: Use to_clk_info() macro for all clocks

* clk-at91:
  clk: at91: sam9x60: support only two programmable clocks
  clk: at91: clk-sam9x60-pll: remove unused variable
  clk: at91: clk-main: update key before writing AT91_CKGR_MOR
  clk: at91: remove the checking of parent_name

* clk-kconfig:
  clk: Restrict CLK_HSDK to ARC_SOC_HSDK

* clk-imx:
  clk: imx8mq: Fix usdhc parents order
  clk: imx: imx21: Remove clock driver
  clk: imx: gate2: Fix a few typos
  clk: imx: Fix and update kerneldoc
  clk: imx: fix i.MX7D peripheral clk mux flags
  clk: imx: fix composite peripheral flags
  clk: imx: Correct the memrepair clock on imx8mp
  clk: imx: Correct the root clk of media ldb on imx8mp
  clk: imx: vf610: Add CRC clock
  clk: imx: Explicitly include bits.h
  clk: imx8qxp: Support building i.MX8QXP clock driver as module
  clk: imx8m: Support module build
  clk: imx: Add clock configuration for ARMv7 platforms
  clk: imx: Support building i.MX common clock driver as module
  clk: composite: Export clk_hw_register_composite()
  clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits

* clk-qcom:
  clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
  clk: qcom: Add display clock controller driver for SM8150 and SM8250
  dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
  clk: qcom: add video clock controller driver for SM8250
  clk: qcom: add video clock controller driver for SM8150
  dt-bindings: clock: add SM8250 QCOM video clock bindings
  dt-bindings: clock: add SM8150 QCOM video clock bindings
  dt-bindings: clock: combine qcom,sdm845-videocc and qcom,sc7180-videocc
  clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs
  clk/qcom: fix spelling typo
  clk: qcom: gcc-sdm660: Fix wrong parent_map
  clk: qcom: dispcc: Update DP clk ops for phy design
  clk: qcom: gcc-msm8939: remove defined but not used variables
  clk: qcom: ipq8074: make pcie0_rchng_clk_src static

* clk-prima2:
  clk: clk-prima2: fix return value check in prima2_clk_init()

* clk-bcm:
  clk: bcm2835: add missing release if devm_clk_hw_register fails
  clk: bcm: rpi: Add register to control pixel bvb clk
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250

maintainers:
  - Jonathan Marek <jonathan@marek.ca>

description: |
  Qualcomm display clock control module which supports the clocks, resets and
  power domains on SM8150 and SM8250.

  See also:
    dt-bindings/clock/qcom,dispcc-sm8150.h
    dt-bindings/clock/qcom,dispcc-sm8250.h

properties:
  compatible:
    enum:
      - qcom,sm8150-dispcc
      - qcom,sm8250-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY0
      - description: Byte clock from DSI PHY1
      - description: Pixel clock from DSI PHY1
      - description: Link clock from DP PHY
      - description: VCO DIV clock from DP PHY

  clock-names:
    items:
      - const: bi_tcxo
      - const: dsi0_phy_pll_out_byteclk
      - const: dsi0_phy_pll_out_dsiclk
      - const: dsi1_phy_pll_out_byteclk
      - const: dsi1_phy_pll_out_dsiclk
      - const: dp_phy_pll_link_clk
      - const: dp_phy_pll_vco_div_clk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@af00000 {
      compatible = "qcom,sm8250-dispcc";
      reg = <0x0af00000 0x10000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&dsi0_phy 0>,
               <&dsi0_phy 1>,
               <&dsi1_phy 0>,
               <&dsi1_phy 1>,
               <&dp_phy 0>,
               <&dp_phy 1>;
      clock-names = "bi_tcxo",
                    "dsi0_phy_pll_out_byteclk",
                    "dsi0_phy_pll_out_dsiclk",
                    "dsi1_phy_pll_out_byteclk",
                    "dsi1_phy_pll_out_dsiclk",
                    "dp_phy_pll_link_clk",
                    "dp_phy_pll_vco_div_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7180-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Video Clock & Reset Controller Binding for SC7180

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm video clock control module which supports the clocks, resets and
  power domains on SC7180.

  See also dt-bindings/clock/qcom,videocc-sc7180.h.

properties:
  compatible:
    const: qcom,sc7180-videocc

  clocks:
    items:
      - description: Board XO source

  clock-names:
    items:
      - const: bi_tcxo

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@ab00000 {
      compatible = "qcom,sc7180-videocc";
      reg = <0x0ab00000 0x10000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>;
      clock-names = "bi_tcxo";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sdm845-videocc.yaml#
$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Video Clock & Reset Controller Binding for SDM845
title: Qualcomm Video Clock & Reset Controller Binding

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm video clock control module which supports the clocks, resets and
  power domains on SDM845.
  power domains on SDM845/SC7180/SM8150/SM8250.

  See also dt-bindings/clock/qcom,videocc-sdm845.h.
  See also:
    dt-bindings/clock/qcom,videocc-sc7180.h
    dt-bindings/clock/qcom,videocc-sdm845.h
    dt-bindings/clock/qcom,videocc-sm8150.h
    dt-bindings/clock/qcom,videocc-sm8250.h

properties:
  compatible:
    const: qcom,sdm845-videocc
    enum:
      - qcom,sc7180-videocc
      - qcom,sdm845-videocc
      - qcom,sm8150-videocc
      - qcom,sm8250-videocc

  clocks:
    items:
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@@ -49,7 +49,7 @@ source "drivers/clk/versatile/Kconfig"

config CLK_HSDK
	bool "PLL Driver for HSDK platform"
	depends on OF || COMPILE_TEST
	depends on ARC_SOC_HSDK || COMPILE_TEST
	depends on HAS_IOMEM
	help
	  This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
+8 −3
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@@ -437,12 +437,17 @@ static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
		return -EINVAL;

	regmap_read(regmap, AT91_CKGR_MOR, &tmp);
	tmp &= ~MOR_KEY_MASK;

	if (index && !(tmp & AT91_PMC_MOSCSEL))
		regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL);
		tmp = AT91_PMC_MOSCSEL;
	else if (!index && (tmp & AT91_PMC_MOSCSEL))
		regmap_write(regmap, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);
		tmp = 0;
	else
		return 0;

	regmap_update_bits(regmap, AT91_CKGR_MOR,
			   AT91_PMC_MOSCSEL | MOR_KEY_MASK,
			   tmp | AT91_PMC_KEY);

	while (!clk_sam9x5_main_ready(regmap))
		cpu_relax();
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