Commit 5eefe5e1 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-5.10-1' of... 

Merge tag 'sunxi-clk-for-5.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Maxime Ripard:

Our usual PR for the Allwinner SoCs, this time adding support for the
Allwinner A100 SoC, and adding support for the sigma-delta modulation on
the audio PLL for the R40.

* tag 'sunxi-clk-for-5.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL
  clk: sunxi-ng: add support for the Allwinner A100 CCU
  dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU
parents 9123e3a7 a3ba99a2

Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml

+6 −1
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@@ -36,6 +36,8 @@ properties: 
      - allwinner,sun9i-a80-ccu

      - allwinner,sun50i-a64-ccu

      - allwinner,sun50i-a64-r-ccu

      - allwinner,sun50i-a100-ccu

      - allwinner,sun50i-a100-r-ccu

      - allwinner,sun50i-h5-ccu

      - allwinner,sun50i-h6-ccu

      - allwinner,sun50i-h6-r-ccu
@@ -78,6 +80,7 @@ if: 
        - allwinner,sun8i-a83t-r-ccu

        - allwinner,sun8i-h3-r-ccu

        - allwinner,sun50i-a64-r-ccu

        - allwinner,sun50i-a100-r-ccu

        - allwinner,sun50i-h6-r-ccu



then:
@@ -94,7 +97,9 @@ else: 
  if:

    properties:

      compatible:

        const: allwinner,sun50i-h6-ccu

        enum:

          - allwinner,sun50i-a100-ccu

          - allwinner,sun50i-h6-ccu



  then:

    properties:

drivers/clk/sunxi-ng/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -17,6 +17,16 @@ config SUN50I_A64_CCU 
	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST



config SUN50I_A100_CCU

	bool "Support for the Allwinner A100 CCU"

	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST



config SUN50I_A100_R_CCU

	bool "Support for the Allwinner A100 PRCM CCU"

	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST



config SUN50I_H6_CCU

	bool "Support for the Allwinner H6 CCU"

	default ARM64 && ARCH_SUNXI

drivers/clk/sunxi-ng/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -23,6 +23,8 @@ obj-y += ccu_mp.o 
# SoC support

obj-$(CONFIG_SUNIV_F1C100S_CCU)	+= ccu-suniv-f1c100s.o

obj-$(CONFIG_SUN50I_A64_CCU)	+= ccu-sun50i-a64.o

obj-$(CONFIG_SUN50I_A100_CCU)	+= ccu-sun50i-a100.o

obj-$(CONFIG_SUN50I_A100_R_CCU)	+= ccu-sun50i-a100-r.o

obj-$(CONFIG_SUN50I_H6_CCU)	+= ccu-sun50i-h6.o

obj-$(CONFIG_SUN50I_H6_R_CCU)	+= ccu-sun50i-h6-r.o

obj-$(CONFIG_SUN4I_A10_CCU)	+= ccu-sun4i-a10.o

drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c

0 → 100644
+214 −0
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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>

 */



#include <linux/clk-provider.h>

#include <linux/module.h>

#include <linux/of_address.h>

#include <linux/platform_device.h>



#include "ccu_common.h"

#include "ccu_reset.h"



#include "ccu_div.h"

#include "ccu_gate.h"

#include "ccu_mp.h"

#include "ccu_nm.h"



#include "ccu-sun50i-a100-r.h"



static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k",

						     "iosc", "pll-periph0" };

static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = {

	{ .index = 3, .shift = 0, .width = 5 },

};



static struct ccu_div r_cpus_clk = {

	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),



	.mux		= {

		.shift	= 24,

		.width	= 2,



		.var_predivs	= cpus_r_apb2_predivs,

		.n_var_predivs	= ARRAY_SIZE(cpus_r_apb2_predivs),

	},



	.common		= {

		.reg		= 0x000,

		.features	= CCU_FEATURE_VARIABLE_PREDIV,

		.hw.init	= CLK_HW_INIT_PARENTS("cpus",

						      cpus_r_apb2_parents,

						      &ccu_div_ops,

						      0),

	},

};



static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);



static struct ccu_div r_apb1_clk = {

	.div		= _SUNXI_CCU_DIV(0, 2),



	.common		= {

		.reg		= 0x00c,

		.hw.init	= CLK_HW_INIT("r-apb1",

					      "r-ahb",

					      &ccu_div_ops,

					      0),

	},

};



static struct ccu_div r_apb2_clk = {

	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),



	.mux		= {

		.shift	= 24,

		.width	= 2,



		.var_predivs	= cpus_r_apb2_predivs,

		.n_var_predivs	= ARRAY_SIZE(cpus_r_apb2_predivs),

	},



	.common		= {

		.reg		= 0x010,

		.features	= CCU_FEATURE_VARIABLE_PREDIV,

		.hw.init	= CLK_HW_INIT_PARENTS("r-apb2",

						      cpus_r_apb2_parents,

						      &ccu_div_ops,

						      0),

	},

};



static const struct clk_parent_data clk_parent_r_apb1[] = {

	{ .hw = &r_apb1_clk.common.hw },

};



static const struct clk_parent_data clk_parent_r_apb2[] = {

	{ .hw = &r_apb2_clk.common.hw },

};



static SUNXI_CCU_GATE_DATA(r_apb1_timer_clk, "r-apb1-timer", clk_parent_r_apb1,

			   0x11c, BIT(0), 0);



static SUNXI_CCU_GATE_DATA(r_apb1_twd_clk, "r-apb1-twd", clk_parent_r_apb1,

			   0x12c, BIT(0), 0);



static const char * const r_apb1_pwm_clk_parents[] = { "dcxo24M", "osc32k",

						       "iosc" };

static SUNXI_CCU_MUX(r_apb1_pwm_clk, "r-apb1-pwm", r_apb1_pwm_clk_parents,

		     0x130, 24, 2, 0);



static SUNXI_CCU_GATE_DATA(r_apb1_bus_pwm_clk, "r-apb1-bus-pwm",

			   clk_parent_r_apb1, 0x13c, BIT(0), 0);



static SUNXI_CCU_GATE_DATA(r_apb1_ppu_clk, "r-apb1-ppu", clk_parent_r_apb1,

			   0x17c, BIT(0), 0);



static SUNXI_CCU_GATE_DATA(r_apb2_uart_clk, "r-apb2-uart", clk_parent_r_apb2,

			   0x18c, BIT(0), 0);



static SUNXI_CCU_GATE_DATA(r_apb2_i2c0_clk, "r-apb2-i2c0", clk_parent_r_apb2,

			   0x19c, BIT(0), 0);



static SUNXI_CCU_GATE_DATA(r_apb2_i2c1_clk, "r-apb2-i2c1", clk_parent_r_apb2,

			   0x19c, BIT(1), 0);



static const char * const r_apb1_ir_rx_parents[] = { "osc32k", "dcxo24M" };

static SUNXI_CCU_MP_WITH_MUX_GATE(r_apb1_ir_rx_clk, "r-apb1-ir-rx",

				  r_apb1_ir_rx_parents, 0x1c0,

				  0, 5,		/* M */

				  8, 2,		/* P */

				  24, 1,	/* mux */

				  BIT(31),	/* gate */

				  0);



static SUNXI_CCU_GATE_DATA(r_apb1_bus_ir_rx_clk, "r-apb1-bus-ir-rx",

			   clk_parent_r_apb1, 0x1cc, BIT(0), 0);



static SUNXI_CCU_GATE(r_ahb_bus_rtc_clk, "r-ahb-rtc", "r-ahb",

		      0x20c, BIT(0), 0);



static struct ccu_common *sun50i_a100_r_ccu_clks[] = {

	&r_cpus_clk.common,

	&r_apb1_clk.common,

	&r_apb2_clk.common,

	&r_apb1_timer_clk.common,

	&r_apb1_twd_clk.common,

	&r_apb1_pwm_clk.common,

	&r_apb1_bus_pwm_clk.common,

	&r_apb1_ppu_clk.common,

	&r_apb2_uart_clk.common,

	&r_apb2_i2c0_clk.common,

	&r_apb2_i2c1_clk.common,

	&r_apb1_ir_rx_clk.common,

	&r_apb1_bus_ir_rx_clk.common,

	&r_ahb_bus_rtc_clk.common,

};



static struct clk_hw_onecell_data sun50i_a100_r_hw_clks = {

	.hws	= {

		[CLK_R_CPUS]		= &r_cpus_clk.common.hw,

		[CLK_R_AHB]		= &r_ahb_clk.hw,

		[CLK_R_APB1]		= &r_apb1_clk.common.hw,

		[CLK_R_APB2]		= &r_apb2_clk.common.hw,

		[CLK_R_APB1_TIMER]	= &r_apb1_timer_clk.common.hw,

		[CLK_R_APB1_TWD]	= &r_apb1_twd_clk.common.hw,

		[CLK_R_APB1_PWM]	= &r_apb1_pwm_clk.common.hw,

		[CLK_R_APB1_BUS_PWM]	= &r_apb1_bus_pwm_clk.common.hw,

		[CLK_R_APB1_PPU]	= &r_apb1_ppu_clk.common.hw,

		[CLK_R_APB2_UART]	= &r_apb2_uart_clk.common.hw,

		[CLK_R_APB2_I2C0]	= &r_apb2_i2c0_clk.common.hw,

		[CLK_R_APB2_I2C1]	= &r_apb2_i2c1_clk.common.hw,

		[CLK_R_APB1_IR]		= &r_apb1_ir_rx_clk.common.hw,

		[CLK_R_APB1_BUS_IR]	= &r_apb1_bus_ir_rx_clk.common.hw,

		[CLK_R_AHB_BUS_RTC]	= &r_ahb_bus_rtc_clk.common.hw,

	},

	.num	= CLK_NUMBER,

};



static struct ccu_reset_map sun50i_a100_r_ccu_resets[] = {

	[RST_R_APB1_TIMER]	=  { 0x11c, BIT(16) },

	[RST_R_APB1_BUS_PWM]	=  { 0x13c, BIT(16) },

	[RST_R_APB1_PPU]	=  { 0x17c, BIT(16) },

	[RST_R_APB2_UART]	=  { 0x18c, BIT(16) },

	[RST_R_APB2_I2C0]	=  { 0x19c, BIT(16) },

	[RST_R_APB2_I2C1]	=  { 0x19c, BIT(17) },

	[RST_R_APB1_BUS_IR]	=  { 0x1cc, BIT(16) },

	[RST_R_AHB_BUS_RTC]	=  { 0x20c, BIT(16) },

};



static const struct sunxi_ccu_desc sun50i_a100_r_ccu_desc = {

	.ccu_clks	= sun50i_a100_r_ccu_clks,

	.num_ccu_clks	= ARRAY_SIZE(sun50i_a100_r_ccu_clks),



	.hw_clks	= &sun50i_a100_r_hw_clks,



	.resets		= sun50i_a100_r_ccu_resets,

	.num_resets	= ARRAY_SIZE(sun50i_a100_r_ccu_resets),

};



static int sun50i_a100_r_ccu_probe(struct platform_device *pdev)

{

	void __iomem *reg;



	reg = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(reg))

		return PTR_ERR(reg);



	return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a100_r_ccu_desc);

}



static const struct of_device_id sun50i_a100_r_ccu_ids[] = {

	{ .compatible = "allwinner,sun50i-a100-r-ccu" },

	{ }

};



static struct platform_driver sun50i_a100_r_ccu_driver = {

	.probe	= sun50i_a100_r_ccu_probe,

	.driver	= {

		.name	= "sun50i-a100-r-ccu",

		.of_match_table	= sun50i_a100_r_ccu_ids,

	},

};

module_platform_driver(sun50i_a100_r_ccu_driver);

drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h

0 → 100644
+21 −0
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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>

 */



#ifndef _CCU_SUN50I_A100_R_H

#define _CCU_SUN50I_A100_R_H



#include <dt-bindings/clock/sun50i-a100-r-ccu.h>

#include <dt-bindings/reset/sun50i-a100-r-ccu.h>



#define CLK_R_CPUS		0

#define CLK_R_AHB		1



/* exported except APB1 for R_PIO */



#define CLK_R_APB2		3



#define CLK_NUMBER	(CLK_R_AHB_BUS_RTC + 1)



#endif /* _CCU_SUN50I_A100_R_H */

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