clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL (a3ba99a2) · Commits · 戴 / test

drivers/clk/sunxi-ng/ccu-sun8i-r40.c

+24 −13

Original line number	Diff line number	Diff line
		@@ -45,15 +45,26 @@ static struct ccu_nkmp pll_cpu_clk = {
		* the base (2x, 4x and 8x), and one variable divider (the one true
		* pll audio).
		*
		* We don't have any need for the variable divider for now, so we just
		* hardcode it to match with the clock names
		* With sigma-delta modulation for fractional-N on the audio PLL,
		* we have to use specific dividers. This means the variable divider
		* can no longer be used, as the audio codec requests the exact clock
		* rates we support through this mechanism. So we now hard code the
		* variable divider to 1. This means the clock rates will no longer
		* match the clock names.
		*/
		#define SUN8I_R40_PLL_AUDIO_REG 0x008

		static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
		static struct ccu_sdm_setting pll_audio_sdm_table[] = {
		{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
		{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
		};

		static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
		"osc24M", 0x008,
		8, 7, /* N */
		0, 5, /* M */
		pll_audio_sdm_table, BIT(24),
		0x284, BIT(31),
		BIT(31), /* gate */
		BIT(28), /* lock */
		CLK_SET_RATE_UNGATE);
		@@ -952,10 +963,10 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
		&pll_audio_base_clk.common.hw
		};

		/* We hardcode the divider to 4 for now */
		/* We hardcode the divider to 1 for now */
		static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
		clk_parent_pll_audio,
		4, 1, CLK_SET_RATE_PARENT);
		1, 1, CLK_SET_RATE_PARENT);
		static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
		clk_parent_pll_audio,
		2, 1, CLK_SET_RATE_PARENT);
		@@ -1307,10 +1318,10 @@ static int sun8i_r40_ccu_probe(struct platform_device *pdev)
		if (IS_ERR(reg))
		return PTR_ERR(reg);

		/* Force the PLL-Audio-1x divider to 4 */
		/* Force the PLL-Audio-1x divider to 1 */
		val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
		val &= ~GENMASK(19, 16);
		writel(val \| (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
		writel(val \| (0 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);

		/* Force PLL-MIPI to MIPI mode */
		val = readl(reg + SUN8I_R40_PLL_MIPI_REG);

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