Commit 5ec06b5c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2020-08-28' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "As expected a bit of an rc3 uptick, amdgpu and msm are the main ones,
  one msm patch was from the merge window, but had dependencies and we
  dropped it until the other tree had landed. Otherwise it's a couple of
  fixes for core, and etnaviv, and single i915, exynos, omap fixes.

  I'm still tracking the Sandybridge gpu relocations issue, if we don't
  see much movement I might just queue up the reverts. I'll talk to
  Daniel next week once he's back from holidays.

  core:
   - Take modeset bkl for legacy drivers

  dp_mst:
   - Allow null crtc in dp_mst

  i915:
   - Fix command parser desc matching with masks

  amdgpu:
   - Misc display fixes
   - Backlight fixes
   - MPO fix for DCN1
   - Fixes for Sienna Cichlid
   - Fixes for Navy Flounder
   - Vega SW CTF fixes
   - SMU fix for Raven
   - Fix a possible overflow in INFO ioctl
   - Gfx10 clockgating fix

  msm:
   - opp/bw scaling patch followup
   - frequency restoring fux
   - vblank in atomic commit fix
   - dpu modesetting fixes
   - fencing fix

  etnaviv:
   - scheduler interaction fix
   - gpu init regression fix

  exynos:
   - Just drop __iommu annotation to fix sparse warning

  omap:
   - locking state fix"

* tag 'drm-fixes-2020-08-28' of git://anongit.freedesktop.org/drm/drm: (41 commits)
  drm/amd/display: Fix memleak in amdgpu_dm_mode_config_init
  drm/amdgpu: disable runtime pm for navy_flounder
  drm/amd/display: Retry AUX write when fail occurs
  drm/amdgpu: Fix buffer overflow in INFO ioctl
  drm/amd/powerplay: Fix hardmins not being sent to SMU for RV
  drm/amdgpu: use MODE1 reset for navy_flounder by default
  drm/amd/pm: correct the thermal alert temperature limit settings
  drm/amdgpu: add asd fw check before loading asd
  drm/amd/display: Keep current gain when ABM disable immediately
  drm/amd/display: Fix passive dongle mistaken as active dongle in EDID emulation
  drm/amd/display: Revert HDCP disable sequence change
  drm/amd/display: Send DISPLAY_OFF after power down on boot
  drm/amdgpu/gfx10: refine mgcg setting
  drm/amd/pm: correct Vega20 swctf limit setting
  drm/amd/pm: correct Vega12 swctf limit setting
  drm/amd/pm: correct Vega10 swctf limit setting
  drm/amd/pm: set VCN pg per instances
  drm/amd/pm: enable run_btc callback for sienna_cichlid
  drivers: gpu: amd: Initialize amdgpu_dm_backlight_caps object to 0 in amdgpu_dm_update_backlight_caps
  drm/amd/display: Reject overlay plane configurations in multi-display scenarios
  ...
parents 15bc20c6 2a3f9da3

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+5 −0
Original line number Diff line number Diff line
@@ -179,6 +179,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 
		case CHIP_VEGA20:

		case CHIP_ARCTURUS:

		case CHIP_SIENNA_CICHLID:

		case CHIP_NAVY_FLOUNDER:

			/* enable runpm if runpm=1 */

			if (amdgpu_runtime_pm > 0)

				adev->runpm = true;
@@ -678,8 +679,12 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
		 * in the bitfields */

		if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)

			se_num = 0xffffffff;

		else if (se_num >= AMDGPU_GFX_MAX_SE)

			return -EINVAL;

		if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)

			sh_num = 0xffffffff;

		else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)

			return -EINVAL;



		if (info->read_mmr_reg.count > 128)

			return -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+1 −2
Original line number Diff line number Diff line
@@ -522,8 +522,7 @@ static int psp_asd_load(struct psp_context *psp) 
	 * add workaround to bypass it for sriov now.

	 * TODO: add version check to make it common

	 */

	if (amdgpu_sriov_vf(psp->adev) ||

	    (psp->adev->asic_type == CHIP_NAVY_FLOUNDER))

	if (amdgpu_sriov_vf(psp->adev) || !psp->asd_fw)

		return 0;



	cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+2 −4
Original line number Diff line number Diff line
@@ -7263,10 +7263,8 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade 
		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |

			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |

			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);



		/* only for Vega10 & Raven1 */

		data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;

			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |

			  RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);



		if (def != data)

			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);

drivers/gpu/drm/amd/amdgpu/nv.c

+1 −0
Original line number Diff line number Diff line
@@ -364,6 +364,7 @@ nv_asic_reset_method(struct amdgpu_device *adev) 


	switch (adev->asic_type) {

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

		return AMD_RESET_METHOD_MODE1;

	default:

		if (smu_baco_is_support(smu))

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+50 −43
Original line number Diff line number Diff line
@@ -2834,12 +2834,18 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 
				    &dm_atomic_state_funcs);



	r = amdgpu_display_modeset_create_props(adev);

	if (r)

	if (r) {

		dc_release_state(state->context);

		kfree(state);

		return r;

	}



	r = amdgpu_dm_audio_init(adev);

	if (r)

	if (r) {

		dc_release_state(state->context);

		kfree(state);

		return r;

	}



	return 0;

}
@@ -2856,6 +2862,8 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) 
#if defined(CONFIG_ACPI)

	struct amdgpu_dm_backlight_caps caps;



	memset(&caps, 0, sizeof(caps));



	if (dm->backlight_caps.caps_valid)

		return;
@@ -2894,51 +2902,50 @@ static int set_backlight_via_aux(struct dc_link *link, uint32_t brightness) 
	return rc ? 0 : 1;

}



static u32 convert_brightness(const struct amdgpu_dm_backlight_caps *caps,

			      const uint32_t user_brightness)

static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,

				unsigned *min, unsigned *max)

{

	u32 min, max, conversion_pace;

	u32 brightness = user_brightness;



	if (!caps)

		goto out;

		return 0;



	if (!caps->aux_support) {

		max = caps->max_input_signal;

		min = caps->min_input_signal;

		/*

		 * The brightness input is in the range 0-255

		 * It needs to be rescaled to be between the

		 * requested min and max input signal

		 * It also needs to be scaled up by 0x101 to

		 * match the DC interface which has a range of

		 * 0 to 0xffff

		 */

		conversion_pace = 0x101;

		brightness =

			user_brightness

			* conversion_pace

			* (max - min)

			/ AMDGPU_MAX_BL_LEVEL

			+ min * conversion_pace;

	if (caps->aux_support) {

		// Firmware limits are in nits, DC API wants millinits.

		*max = 1000 * caps->aux_max_input_signal;

		*min = 1000 * caps->aux_min_input_signal;

	} else {

		/* TODO

		 * We are doing a linear interpolation here, which is OK but

		 * does not provide the optimal result. We probably want

		 * something close to the Perceptual Quantizer (PQ) curve.

		 */

		max = caps->aux_max_input_signal;

		min = caps->aux_min_input_signal;

		// Firmware limits are 8-bit, PWM control is 16-bit.

		*max = 0x101 * caps->max_input_signal;

		*min = 0x101 * caps->min_input_signal;

	}

	return 1;

}



static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,

					uint32_t brightness)

{

	unsigned min, max;



	if (!get_brightness_range(caps, &min, &max))

		return brightness;



		brightness = (AMDGPU_MAX_BL_LEVEL - user_brightness) * min

			       + user_brightness * max;

		// Multiple the value by 1000 since we use millinits

		brightness *= 1000;

		brightness = DIV_ROUND_CLOSEST(brightness, AMDGPU_MAX_BL_LEVEL);

	// Rescale 0..255 to min..max

	return min + DIV_ROUND_CLOSEST((max - min) * brightness,

				       AMDGPU_MAX_BL_LEVEL);

}



out:

static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,

				      uint32_t brightness)

{

	unsigned min, max;



	if (!get_brightness_range(caps, &min, &max))

		return brightness;



	if (brightness < min)

		return 0;

	// Rescale min..max to 0..255

	return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),

				 max - min);

}



static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
@@ -2954,7 +2961,7 @@ static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 


	link = (struct dc_link *)dm->backlight_link;



	brightness = convert_brightness(&caps, bd->props.brightness);

	brightness = convert_brightness_from_user(&caps, bd->props.brightness);

	// Change brightness based on AUX property

	if (caps.aux_support)

		return set_backlight_via_aux(link, brightness);
@@ -2971,7 +2978,7 @@ static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 


	if (ret == DC_ERROR_UNEXPECTED)

		return bd->props.brightness;

	return ret;

	return convert_brightness_to_user(&dm->backlight_caps, ret);

}



static const struct backlight_ops amdgpu_dm_backlight_ops = {

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