Merge tag 'drm-intel-fixes-2020-08-27' of... (2a3f9da3) · Commits · 戴 / test

drivers/gpu/drm/i915/i915_cmd_parser.c

+10 −4

Original line number	Diff line number	Diff line
		@@ -1204,6 +1204,12 @@ static u32 copy_batch(struct drm_i915_gem_object dst_obj,
		return dst;
		}

		static inline bool cmd_desc_is(const struct drm_i915_cmd_descriptor * const desc,
		const u32 cmd)
		{
		return desc->cmd.value == (cmd & desc->cmd.mask);
		}

		static bool check_cmd(const struct intel_engine_cs *engine,
		const struct drm_i915_cmd_descriptor *desc,
		const u32 *cmd, u32 length)
		@@ -1242,19 +1248,19 @@ static bool check_cmd(const struct intel_engine_cs *engine,
		* allowed mask/value pair given in the whitelist entry.
		*/
		if (reg->mask) {
		if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
		if (cmd_desc_is(desc, MI_LOAD_REGISTER_MEM)) {
		DRM_DEBUG("CMD: Rejected LRM to masked register 0x%08X\n",
		reg_addr);
		return false;
		}

		if (desc->cmd.value == MI_LOAD_REGISTER_REG) {
		if (cmd_desc_is(desc, MI_LOAD_REGISTER_REG)) {
		DRM_DEBUG("CMD: Rejected LRR to masked register 0x%08X\n",
		reg_addr);
		return false;
		}

		if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
		if (cmd_desc_is(desc, MI_LOAD_REGISTER_IMM(1)) &&
		(offset + 2 > length \|\|
		(cmd[offset + 1] & reg->mask) != reg->value)) {
		DRM_DEBUG("CMD: Rejected LRI to masked register 0x%08X\n",
		@@ -1478,7 +1484,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
		break;
		}

		if (desc->cmd.value == MI_BATCH_BUFFER_START) {
		if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) {
		ret = check_bbstart(cmd, offset, length, batch_length,
		batch_addr, shadow_addr,
		jump_whitelist);