Commit 5ebb34ed authored by Peter Zijlstra's avatar Peter Zijlstra
Browse files

x86/intel: Aggregate microserver naming 



Currently big microservers have _XEON_D while small microservers have
_X, Make it uniformly: _D.

for i in `git grep -l "\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6\).*_\(X\|XEON_D\)"`
do
	sed -i -e 's/\(\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6\).*ATOM.*\)_X/\1_D/g' \
	       -e 's/\(\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6\).*\)_XEON_D/\1_D/g' ${i}
done

Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarTony Luck <tony.luck@intel.com>
Cc: x86@kernel.org
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Borislav Petkov <bp@alien8.de>
Link: https://lkml.kernel.org/r/20190827195122.677152989@infradead.org
parent 5e741407

arch/x86/events/intel/core.c

+10 −10
Original line number Diff line number Diff line
@@ -3971,10 +3971,10 @@ static const struct x86_cpu_desc isolation_ucodes[] = { 
	INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,		 4, 0x0000000a),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL,		 4, 0x00000023),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G,		 1, 0x00000014),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D,	 2, 0x00000010),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D,	 3, 0x07000009),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D,	 4, 0x0f000009),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D,	 5, 0x0e000002),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,		 2, 0x00000010),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,		 3, 0x07000009),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,		 4, 0x0f000009),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,		 5, 0x0e000002),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X,		 2, 0x0b000014),

	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,		 3, 0x00000021),

	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,		 4, 0x00000000),
@@ -4146,7 +4146,7 @@ static const struct x86_cpu_desc counter_freezing_ucodes[] = { 
	INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT,	 2, 0x0000000e),

	INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT,	 9, 0x0000002e),

	INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT,	10, 0x00000008),

	INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_X,	 1, 0x00000028),

	INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_D,	 1, 0x00000028),

	INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS,	 1, 0x00000028),

	INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS,	 8, 0x00000006),

	{}
@@ -4643,7 +4643,7 @@ __init int intel_pmu_init(void) 
		break;



	case INTEL_FAM6_ATOM_SILVERMONT:

	case INTEL_FAM6_ATOM_SILVERMONT_X:

	case INTEL_FAM6_ATOM_SILVERMONT_D:

	case INTEL_FAM6_ATOM_SILVERMONT_MID:

	case INTEL_FAM6_ATOM_AIRMONT:

	case INTEL_FAM6_ATOM_AIRMONT_MID:
@@ -4665,7 +4665,7 @@ __init int intel_pmu_init(void) 
		break;



	case INTEL_FAM6_ATOM_GOLDMONT:

	case INTEL_FAM6_ATOM_GOLDMONT_X:

	case INTEL_FAM6_ATOM_GOLDMONT_D:

		x86_add_quirk(intel_counter_freezing_quirk);

		memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));
@@ -4721,7 +4721,7 @@ __init int intel_pmu_init(void) 
		name = "goldmont_plus";

		break;



	case INTEL_FAM6_ATOM_TREMONT_X:

	case INTEL_FAM6_ATOM_TREMONT_D:

		x86_pmu.late_ack = true;

		memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));
@@ -4891,7 +4891,7 @@ __init int intel_pmu_init(void) 
		break;



	case INTEL_FAM6_BROADWELL:

	case INTEL_FAM6_BROADWELL_XEON_D:

	case INTEL_FAM6_BROADWELL_D:

	case INTEL_FAM6_BROADWELL_G:

	case INTEL_FAM6_BROADWELL_X:

		x86_add_quirk(intel_pebs_isolation_quirk);
@@ -5002,7 +5002,7 @@ __init int intel_pmu_init(void) 
		break;



	case INTEL_FAM6_ICELAKE_X:

	case INTEL_FAM6_ICELAKE_XEON_D:

	case INTEL_FAM6_ICELAKE_D:

		pmem = true;

		/* fall through */

	case INTEL_FAM6_ICELAKE_L:

arch/x86/events/intel/cstate.c

+6 −6
Original line number Diff line number Diff line
@@ -600,11 +600,11 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_L, hswult_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT,   slm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT_X, slm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT_D, slm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT,      slm_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL,   snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_XEON_D, snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_D, snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_G, snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_X, snb_cstates),
@@ -621,7 +621,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT,   glm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_X, glm_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_D, glm_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),

arch/x86/events/intel/pt.c

+1 −1
Original line number Diff line number Diff line
@@ -205,7 +205,7 @@ static int __init pt_pmu_hw_init(void) 
	/* model-specific quirks */

	switch (boot_cpu_data.x86_model) {

	case INTEL_FAM6_BROADWELL:

	case INTEL_FAM6_BROADWELL_XEON_D:

	case INTEL_FAM6_BROADWELL_D:

	case INTEL_FAM6_BROADWELL_G:

	case INTEL_FAM6_BROADWELL_X:

		/* not setting BRANCH_EN will #GP, erratum BDM106 */

arch/x86/events/intel/rapl.c

+2 −2
Original line number Diff line number Diff line
@@ -727,7 +727,7 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = { 
	X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL,		model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_G,		model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_X,		model_hsx),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D,	model_hsx),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_D,		model_hsx),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL,		model_knl),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNM,		model_knl),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_L,		model_skl),
@@ -737,7 +737,7 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = { 
	X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE,		model_skl),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_L,		model_skl),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT,		model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT_X,	model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT_D,	model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT_PLUS,	model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ICELAKE_L,		model_skl),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_ICELAKE,		model_skl),

arch/x86/events/intel/uncore.c

+2 −2
Original line number Diff line number Diff line
@@ -1462,7 +1462,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = { 
	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE_X,	  ivbep_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_X,	  hswep_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_X,	  bdx_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, bdx_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_D,	  bdx_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL,	  knl_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNM,	  knl_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE,	  skl_uncore_init),
@@ -1473,7 +1473,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = { 
	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_ICELAKE_L,	  icl_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_ICELAKE_NNPI,	  icl_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_ICELAKE,	  icl_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_ATOM_TREMONT_X, snr_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_ATOM_TREMONT_D, snr_uncore_init),

	{},

};

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