Commit 5e741407 authored by Peter Zijlstra's avatar Peter Zijlstra
Browse files

x86/intel: Aggregate big core graphics naming 



Currently big core clients with extra graphics on have:

 - _G
 - _GT3E

Make it uniformly: _G

for i in `git grep -l "\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6\).*_GT3E"`
do
	sed -i -e 's/\(\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6\).*\)_GT3E/\1_G/g' ${i}
done

Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarTony Luck <tony.luck@intel.com>
Cc: x86@kernel.org
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Borislav Petkov <bp@alien8.de>
Link: https://lkml.kernel.org/r/20190827195122.622802314@infradead.org
parent af239c44

arch/x86/events/intel/core.c

+4 −4
Original line number Diff line number Diff line
@@ -3966,11 +3966,11 @@ static __init void intel_clovertown_quirk(void) 
static const struct x86_cpu_desc isolation_ucodes[] = {

	INTEL_CPU_DESC(INTEL_FAM6_HASWELL,		 3, 0x0000001f),

	INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L,		 1, 0x0000001e),

	INTEL_CPU_DESC(INTEL_FAM6_HASWELL_GT3E,		 1, 0x00000015),

	INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G,		 1, 0x00000015),

	INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,		 2, 0x00000037),

	INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,		 4, 0x0000000a),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL,		 4, 0x00000023),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_GT3E,	 1, 0x00000014),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G,		 1, 0x00000014),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D,	 2, 0x00000010),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D,	 3, 0x07000009),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D,	 4, 0x0f000009),
@@ -4860,7 +4860,7 @@ __init int intel_pmu_init(void) 
	case INTEL_FAM6_HASWELL:

	case INTEL_FAM6_HASWELL_X:

	case INTEL_FAM6_HASWELL_L:

	case INTEL_FAM6_HASWELL_GT3E:

	case INTEL_FAM6_HASWELL_G:

		x86_add_quirk(intel_ht_bug);

		x86_add_quirk(intel_pebs_isolation_quirk);

		x86_pmu.late_ack = true;
@@ -4892,7 +4892,7 @@ __init int intel_pmu_init(void) 


	case INTEL_FAM6_BROADWELL:

	case INTEL_FAM6_BROADWELL_XEON_D:

	case INTEL_FAM6_BROADWELL_GT3E:

	case INTEL_FAM6_BROADWELL_G:

	case INTEL_FAM6_BROADWELL_X:

		x86_add_quirk(intel_pebs_isolation_quirk);

		x86_pmu.late_ack = true;

arch/x86/events/intel/cstate.c

+4 −4
Original line number Diff line number Diff line
@@ -595,7 +595,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 


	X86_CSTATES_MODEL(INTEL_FAM6_HASWELL,   snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_X, snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_GT3E, snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_G, snb_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_L, hswult_cstates),
@@ -605,7 +605,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 


	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL,        snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_XEON_D, snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_GT3E,   snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_G,      snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_X,      snb_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_L, snb_cstates),

arch/x86/events/intel/pt.c

+1 −1
Original line number Diff line number Diff line
@@ -206,7 +206,7 @@ static int __init pt_pmu_hw_init(void) 
	switch (boot_cpu_data.x86_model) {

	case INTEL_FAM6_BROADWELL:

	case INTEL_FAM6_BROADWELL_XEON_D:

	case INTEL_FAM6_BROADWELL_GT3E:

	case INTEL_FAM6_BROADWELL_G:

	case INTEL_FAM6_BROADWELL_X:

		/* not setting BRANCH_EN will #GP, erratum BDM106 */

		pt_pmu.branch_en_always_on = true;

arch/x86/events/intel/rapl.c

+2 −2
Original line number Diff line number Diff line
@@ -723,9 +723,9 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = { 
	X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL,		model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_X,		model_hsx),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_L,		model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_GT3E,		model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_G,		model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL,		model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_GT3E,		model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_G,		model_hsw),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_X,		model_hsx),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D,	model_hsx),

	X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL,		model_knl),

arch/x86/events/intel/uncore.c

+2 −2
Original line number Diff line number Diff line
@@ -1453,9 +1453,9 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = { 
	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE,	  ivb_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL,	  hsw_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_L,	  hsw_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_GT3E,	  hsw_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_G,	  hsw_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL,	  bdw_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_GT3E, bdw_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_G,	  bdw_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE_X,  snbep_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_NEHALEM_EX,	  nhmex_uncore_init),

	X86_UNCORE_MODEL_MATCH(INTEL_FAM6_WESTMERE_EX,	  nhmex_uncore_init),

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