Unverified Commit 5de39aca authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard
Browse files

clk: sunxi-ng: a64: Add max. rate constraint to video PLLs 



Video PLLs on A64 can be set to higher rate that it is actually
supported by HW.

Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
clock driver. Interestengly, user manual specifies maximum frequency to
be 600 MHz. Historically, this data was wrong in some user manuals for
other SoCs, so more faith is put in BSP clock driver.

Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent 65b1e8a6

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+26 −24
Original line number Diff line number Diff line
@@ -64,9 +64,10 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 
				   BIT(28),	/* lock */

				   CLK_SET_RATE_UNGATE);



static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",

						"osc24M", 0x010,

						192000000,	/* Minimum rate */

						1008000000,	/* Maximum rate */

						8, 7,		/* N */

						0, 4,		/* M */

						BIT(24),	/* frac enable */
@@ -126,9 +127,10 @@ static struct ccu_nk pll_periph1_clk = { 
	},

};



static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",

						"osc24M", 0x030,

						192000000,	/* Minimum rate */

						1008000000,	/* Maximum rate */

						8, 7,		/* N */

						0, 4,		/* M */

						BIT(24),	/* frac enable */

CRA Git | Maintained and supported by SUSTech CRA and CCSE