clk: sunxi-ng: a64: Add minimal rate for video PLLs (65b1e8a6) · Commits · 戴 / test

According to documentation and experience with other similar SoCs, video PLLs don't work stable if their output frequency is set below 192 MHz. Because of that, set minimal rate to both A64 video PLLs to 192 MHz. Signed-off-by:

Jagan Teki <jagan@amarulasolutions.com> Signed-off-by:

Icenowy Zheng <icenowy@aosc.io> Reviewed-by:

Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by:

Maxime Ripard <maxime.ripard@bootlin.com>

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+24 −22

Original line number	Diff line number	Diff line
		@@ -64,8 +64,9 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
		BIT(28), /* lock */
		CLK_SET_RATE_UNGATE);

		static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
		static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
		"osc24M", 0x010,
		192000000, /* Minimum rate */
		8, 7, /* N */
		0, 4, /* M */
		BIT(24), /* frac enable */
		@@ -125,8 +126,9 @@ static struct ccu_nk pll_periph1_clk = {
		},
		};

		static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
		static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
		"osc24M", 0x030,
		192000000, /* Minimum rate */
		8, 7, /* N */
		0, 4, /* M */
		BIT(24), /* frac enable */

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