Commit 5d869230 authored by Michel Thierry's avatar Michel Thierry Committed by Lucas De Marchi
Browse files

drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating 



HCP/MFX power gating is disabled by default, turn it on for the vd units
available. User space will also issue a MI_FORCE_WAKEUP properly to
wake up proper subwell.

During driver load, init_clock_gating happens after device_info_init_mmio
read the vdbox disable fuse register, so only present vd units will have
these enabled.

BSpec: 14214
HSDES: 1209977827
Signed-off-by: default avatarMichel Thierry <michel.thierry@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarTony Ye <tony.ye@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190823082055.5992-3-lucas.demarchi@intel.com
parent b3c0692f

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -8615,6 +8615,10 @@ enum { 
#define   GEN9_PWRGT_MEDIA_STATUS_MASK		(1 << 0)

#define   GEN9_PWRGT_RENDER_STATUS_MASK		(1 << 1)



#define POWERGATE_ENABLE			_MMIO(0xa210)

#define    VDN_HCP_POWERGATE_ENABLE(n)		BIT(((n) * 2) + 3)

#define    VDN_MFX_POWERGATE_ENABLE(n)		BIT(((n) * 2) + 4)



#define  GTFIFODBG				_MMIO(0x120000)

#define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV	(0x1f << 20)

#define    GT_FIFO_FREE_ENTRIES_CHV		(0x7f << 13)

drivers/gpu/drm/i915/intel_pm.c

+17 −1
Original line number Diff line number Diff line
@@ -9078,6 +9078,22 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv) 
		   _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));

}



static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)

{

	u32 vd_pg_enable = 0;

	unsigned int i;



	/* This is not a WA. Enable VD HCP & MFX_ENC powergate */

	for (i = 0; i < I915_MAX_VCS; i++) {

		if (HAS_ENGINE(dev_priv, _VCS(i)))

			vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |

					VDN_MFX_POWERGATE_ENABLE(i);

	}



	I915_WRITE(POWERGATE_ENABLE,

		   I915_READ(POWERGATE_ENABLE) | vd_pg_enable);

}



static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)

{

	if (!HAS_PCH_CNP(dev_priv))
@@ -9598,7 +9614,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) 
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)

{

	if (IS_GEN(dev_priv, 12))

		dev_priv->display.init_clock_gating = nop_init_clock_gating;

		dev_priv->display.init_clock_gating = tgl_init_clock_gating;

	else if (IS_GEN(dev_priv, 11))

		dev_priv->display.init_clock_gating = icl_init_clock_gating;

	else if (IS_CANNONLAKE(dev_priv))

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