drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap (b3c0692f) · Commits · 戴 / test

GAM registers located in the 0x4xxx range have been relocated to 0xCxxx; this is to make space for global MOCS registers. v2: Rename register and bitfield to its new name (suggested by Mika) HSD: 399379 Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:

Michel Thierry <michel.thierry@intel.com> Reviewed-by:

Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:

Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by:

Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190823082055.5992-2-lucas.demarchi@intel.com

drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -83,6 +83,9 @@
		#define GEN8_GTCR _MMIO(0x4274)
		#define GEN8_GTCR_INVALIDATE (1<<0)

		#define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8)
		#define GEN12_GUC_TLB_INV_CR_INVALIDATE (1 << 0)

		#define GUC_ARAT_C6DIS _MMIO(0xA178)

		#define GUC_SHIM_CONTROL _MMIO(0xc064)

drivers/gpu/drm/i915/i915_gem_gtt.c

+7 −1

Original line number	Diff line number	Diff line
		@@ -132,8 +132,14 @@ static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
		static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
		{
		struct intel_uncore *uncore = ggtt->vm.gt->uncore;
		struct drm_i915_private *i915 = ggtt->vm.i915;

		gen6_ggtt_invalidate(ggtt);

		if (INTEL_GEN(i915) >= 12)
		intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
		GEN12_GUC_TLB_INV_CR_INVALIDATE);
		else
		intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
		}

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