Commit 5d867ab0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2019-11-22' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Two sets of fixes in here, one for amdgpu, and one for i915.

  The amdgpu ones are pretty small, i915's CI system seems to have a few
  problems in the last week or so, there is one major regression fix for
  fb_mmap, but there are a bunch of other issues fixed in there as well,
  oops, screen flashes and rcu related.

  amdgpu:
   - Remove experimental flag for navi14
   - Fix confusing power message failures on older VI parts
   - Hang fix for gfxoff when using the read register interface
   - Two stability regression fixes for Raven

  i915:
   - Fix kernel oops on dumb_create ioctl on no crtc situation
   - Fix bad ugly colored flash on VLV/CHV related to gamma LUT update
   - Fix unity of the frequencies reported on PMU
   - Fix kernel oops on set_page_dirty using better locks around it
   - Protect the request pointer with RCU to prevent it being freed
     while we might need still
   - Make pool objects read-only
   - Restore physical addresses for fb_map to avoid corrupted page
     table"

* tag 'drm-fixes-2019-11-22' of git://anongit.freedesktop.org/drm/drm:
  drm/i915/fbdev: Restore physical addresses for fb_mmap()
  Revert "drm/amd/display: enable S/G for RAVEN chip"
  drm/amdgpu: disable gfxoff on original raven
  drm/amdgpu: disable gfxoff when using register read interface
  drm/amd/powerplay: correct fine grained dpm force level setting
  drm/amd/powerplay: issue no PPSMC_MSG_GetCurrPkgPwr on unsupported ASICs
  drm/amdgpu: remove experimental flag for Navi14
  drm/i915: make pool objects read-only
  drm/i915: Protect request peeking with RCU
  drm/i915/userptr: Try to acquire the page lock around set_page_dirty()
  drm/i915/pmu: "Frequency" is reported as accumulated cycles
  drm/i915: Preload LUTs if the hw isn't currently using them
  drm/i915: Don't oops in dumb_create ioctl if we have no crtcs
parents 81429eb8 51658c04

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+1 −1
Original line number Diff line number Diff line
@@ -511,7 +511,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, 
	 * Also, don't allow GTT domain if the BO doens't have USWC falg set.

	 */

	if (adev->asic_type >= CHIP_CARRIZO &&

	    adev->asic_type <= CHIP_RAVEN &&

	    adev->asic_type < CHIP_RAVEN &&

	    (adev->flags & AMD_IS_APU) &&

	    (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&

	    amdgpu_bo_support_uswc(bo_flags) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+4 −4
Original line number Diff line number Diff line
@@ -1013,10 +1013,10 @@ static const struct pci_device_id pciidlist[] = { 
	{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},

	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},

	/* Navi14 */

	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},

	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},

	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},

	{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},

	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},

	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},

	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},

	{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},



	/* Renoir */

	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+5 −1
Original line number Diff line number Diff line
@@ -649,15 +649,19 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
			return -ENOMEM;

		alloc_size = info->read_mmr_reg.count * sizeof(*regs);



		for (i = 0; i < info->read_mmr_reg.count; i++)

		amdgpu_gfx_off_ctrl(adev, false);

		for (i = 0; i < info->read_mmr_reg.count; i++) {

			if (amdgpu_asic_read_register(adev, se_num, sh_num,

						      info->read_mmr_reg.dword_offset + i,

						      &regs[i])) {

				DRM_DEBUG_KMS("unallowed offset %#x\n",

					      info->read_mmr_reg.dword_offset + i);

				kfree(regs);

				amdgpu_gfx_off_ctrl(adev, true);

				return -EFAULT;

			}

		}

		amdgpu_gfx_off_ctrl(adev, true);

		n = copy_to_user(out, regs, min(size, alloc_size));

		kfree(regs);

		return n ? -EFAULT : 0;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+7 −2
Original line number Diff line number Diff line
@@ -1038,7 +1038,12 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) 
	case CHIP_VEGA20:

		break;

	case CHIP_RAVEN:

		if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)

		/* Disable GFXOFF on original raven.  There are combinations

		 * of sbios and platforms that are not stable.

		 */

		if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8))

			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;

		else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)

			 &&((adev->gfx.rlc_fw_version != 106 &&

			     adev->gfx.rlc_fw_version < 531) ||

			    (adev->gfx.rlc_fw_version == 53815) ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+1 −1
Original line number Diff line number Diff line
@@ -688,7 +688,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) 
	 */

	if (adev->flags & AMD_IS_APU &&

	    adev->asic_type >= CHIP_CARRIZO &&

	    adev->asic_type <= CHIP_RAVEN)

	    adev->asic_type < CHIP_RAVEN)

		init_data.flags.gpu_vm_support = true;



	if (amdgpu_dc_feature_mask & DC_FBC_MASK)

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