Commit 5b8c5969 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.11-2020-11-05' of git://people.freedesktop.org/~agd5f/linux into drm-next 

amd-drm-next-5.11-2020-11-05:

amdgpu:
- Add initial support for Vangogh
- Add support for Green Sardine
- Add initial support for Dimgrey Cavefish
- Scatter/Gather display support for Renoir
- Updates for Sienna Cichlid
- Updates for Navy Flounder
- SMU7 power improvements
- Modifier support for gfx9+
- CI BACO fixes
- Arcturus SMU fixes
- Lots of code cleanups
- DC fixes
- Kernel doc fixes
- Add more GPU HW client information to page fault error logging
- MPO clock tuning for RV
- FP fixes for DCN3 on ARM and PPC

radeon:
- Expose voltage via hwmon on Sumo APUs

amdkfd:
- Fix unique id handling
- Misc fixes

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201105222749.201798-1-alexander.deucher@amd.com
parents c0f98d2f 514ad1b6

MAINTAINERS

+1 −1
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@@ -934,7 +934,7 @@ M: Evan Quan <evan.quan@amd.com> 
L:	amd-gfx@lists.freedesktop.org

S:	Supported

T:	git git://people.freedesktop.org/~agd5f/linux

F:	drivers/gpu/drm/amd/powerplay/

F:	drivers/gpu/drm/amd/pm/powerplay/















AMD SEATTLE DEVICE TREE SUPPORT















M:	Brijesh Singh <brijeshkumar.singh@amd.com>

































drivers/gpu/drm/amd/amdgpu/Makefile



+5
−3






























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@@ -55,7 +55,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \













	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \















	amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \















	amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \













	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o













	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \













	amdgpu_fw_attestation.o































amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o

























@@ -69,7 +70,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce













amdgpu-y += \















	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \















	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \













	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o













	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \













	nbio_v7_2.o dimgrey_cavefish_reg_init.o































# add DF block















amdgpu-y += \









@@ -81,7 +83,7 @@ amdgpu-y += \













	gmc_v7_0.o \















	gmc_v8_0.o \















	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \













	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o













	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o































# add UMC block















amdgpu-y += \

































drivers/gpu/drm/amd/amdgpu/amdgpu.h



+43
−13






























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@@ -623,6 +623,8 @@ struct amdgpu_asic_funcs {













	bool (*supports_baco)(struct amdgpu_device *adev);















	/* pre asic_init quirks */















	void (*pre_asic_init)(struct amdgpu_device *adev);













	/* enter/exit umd stable pstate */













	int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);















};































/*










@@ -723,6 +725,45 @@ struct amd_powerplay {













	const struct amd_pm_funcs *pp_funcs;















};





























/* polaris10 kickers */













#define ASICID_IS_P20(did, rid)		(((did == 0x67DF) && \













					 ((rid == 0xE3) || \













					  (rid == 0xE4) || \













					  (rid == 0xE5) || \













					  (rid == 0xE7) || \













					  (rid == 0xEF))) || \













					 ((did == 0x6FDF) && \













					 ((rid == 0xE7) || \













					  (rid == 0xEF) || \













					  (rid == 0xFF))))



























#define ASICID_IS_P30(did, rid)		((did == 0x67DF) && \













					((rid == 0xE1) || \













					 (rid == 0xF7)))



























/* polaris11 kickers */













#define ASICID_IS_P21(did, rid)		(((did == 0x67EF) && \













					 ((rid == 0xE0) || \













					  (rid == 0xE5))) || \













					 ((did == 0x67FF) && \













					 ((rid == 0xCF) || \













					  (rid == 0xEF) || \













					  (rid == 0xFF))))



























#define ASICID_IS_P31(did, rid)		((did == 0x67EF) && \













					((rid == 0xE2)))



























/* polaris12 kickers */













#define ASICID_IS_P23(did, rid)		(((did == 0x6987) && \













					 ((rid == 0xC0) || \













					  (rid == 0xC1) || \













					  (rid == 0xC3) || \













					  (rid == 0xC7))) || \













					 ((did == 0x6981) && \













					 ((rid == 0x00) || \













					  (rid == 0x01) || \













					  (rid == 0x10))))





























#define AMDGPU_RESET_MAGIC_NUM 64















#define AMDGPU_MAX_DF_PERFMONS 4















struct amdgpu_device {










@@ -1165,6 +1206,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);













#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))















#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))















#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))













#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \













	((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)































#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));


























@@ -1294,19 +1337,6 @@ bool amdgpu_device_load_pci_state(struct pci_dev *pdev);





























#include "amdgpu_object.h"





























/* used by df_v3_6.c and amdgpu_pmu.c */













#define AMDGPU_PMU_ATTR(_name, _object)					\













static ssize_t								\













_name##_show(struct device *dev,					\













			       struct device_attribute *attr,		\













			       char *page)				\













{									\













	BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1);			\













	return sprintf(page, _object "\n");				\













}									\













									\













static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)





























static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)















{















       return adev->gmc.tmz_enabled;

































drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c



+14
−13






























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@@ -390,23 +390,17 @@ void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,













				      struct kfd_local_mem_info *mem_info)















{















	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;













	uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :













					     ~((1ULL << 32) - 1);













	resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;































	memset(mem_info, 0, sizeof(*mem_info));













	if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {





























	mem_info->local_mem_size_public = adev->gmc.visible_vram_size;















	mem_info->local_mem_size_private = adev->gmc.real_vram_size -















						adev->gmc.visible_vram_size;













	} else {













		mem_info->local_mem_size_public = 0;













		mem_info->local_mem_size_private = adev->gmc.real_vram_size;













	}





























	mem_info->vram_width = adev->gmc.vram_width;





























	pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",













			&adev->gmc.aper_base, &aper_limit,













	pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",













			&adev->gmc.aper_base,















			mem_info->local_mem_size_public,















			mem_info->local_mem_size_private);


























@@ -648,6 +642,13 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)













{















	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;





























	/* Temp workaround to fix the soft hang observed in certain compute













	 * applications if GFXOFF is enabled.













	 */













	if (adev->asic_type == CHIP_SIENNA_CICHLID) {













		pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");













		amdgpu_gfx_off_ctrl(adev, idle);













	}















	amdgpu_dpm_switch_power_profile(adev,















					PP_SMC_POWER_PROFILE_COMPUTE,















					!idle);

































drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c



+1
−0






























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@@ -304,4 +304,5 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = {













				kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,















	.set_vm_context_page_table_base =















				kgd_gfx_v9_set_vm_context_page_table_base,













	.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy















};
































































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