Commit 5a96c5d0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/pub/scm/linux/kernel/git/willy/parisc-2.6 

* master.kernel.org:/pub/scm/linux/kernel/git/willy/parisc-2.6: (41 commits)
  [PARISC] Kill wall_jiffies use
  [PARISC] Honour "panic_on_oops" sysctl
  [PARISC] Fix fs/binfmt_som.c
  [PARISC] Export clear_user_page to modules
  [PARISC] Make DMA routines more stubby
  [PARISC] Define pci_get_legacy_ide_irq
  [PARISC] Fix CONFIG_DEBUG_SPINLOCK
  [PARISC] Fix HPUX compat compile with current GCC
  [PARISC] Fix iounmap compile warning
  [PARISC] Add support for Quicksilver AGPGART
  [PARISC] Move LBA and SBA register defines to the common ropes.h
  [PARISC] Create shared <asm/ropes.h> header
  [PARISC] Stash the lba_device in its struct device drvdata
  [PARISC] Generalize IS_ASTRO et al to take a parisc_device like
  [PARISC] Pretty print the name of the lba type on kernel boot
  [PARISC] Remove some obsolete comments and I checked that Reo is similar to Ike
  [PARISC] Add hardware found in the rp8400
  [PARISC] Allow nested interrupts
  [PARISC] Further updates to timer_interrupt()
  [PARISC] remove halftick and copy clocktick to local var (gcc can optimize usage)
  ...
parents 13bbd8d9 5f024a25

arch/parisc/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ config PA11 


config PREFETCH

	def_bool y

	depends on PA8X00

	depends on PA8X00 || PA7200



config 64BIT

	bool "64-bit kernel"

arch/parisc/hpux/fs.c

+1 −1
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ static int filldir(void * __buf, const char * name, int namlen, loff_t offset, 
	put_user(namlen, &dirent->d_namlen);

	copy_to_user(dirent->d_name, name, namlen);

	put_user(0, dirent->d_name + namlen);

	((char *) dirent) += reclen;

	dirent = (void __user *)dirent + reclen;

	buf->current_dir = dirent;

	buf->count -= reclen;

	return 0;

arch/parisc/kernel/binfmt_elf32.c

+1 −23
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ struct elf_prpsinfo32 
 */



#define SET_PERSONALITY(ex, ibcs2) \

	current->personality = PER_LINUX32; \

	set_thread_flag(TIF_32BIT); \

	current->thread.map_base = DEFAULT_MAP_BASE32; \

	current->thread.task_size = DEFAULT_TASK_SIZE32 \
@@ -102,25 +102,3 @@ cputime_to_compat_timeval(const cputime_t cputime, struct compat_timeval *value) 
}



#include "../../../fs/binfmt_elf.c"
 


/* Set up a separate execution domain for ELF32 binaries running

 * on an ELF64 kernel */



static struct exec_domain parisc32_exec_domain = { 

	.name = "Linux/ELF32",

	.pers_low = PER_LINUX32,

	.pers_high = PER_LINUX32,

};      



static int __init parisc32_exec_init(void)

{

	/* steal the identity signal mappings from the default domain */

	parisc32_exec_domain.signal_map = default_exec_domain.signal_map;

	parisc32_exec_domain.signal_invmap = default_exec_domain.signal_invmap;



	register_exec_domain(&parisc32_exec_domain);



	return 0;

}



__initcall(parisc32_exec_init);

arch/parisc/kernel/cache.c

+44 −4
Original line number Diff line number Diff line
@@ -35,15 +35,12 @@ int icache_stride __read_mostly; 
EXPORT_SYMBOL(dcache_stride);





#if defined(CONFIG_SMP)

/* On some machines (e.g. ones with the Merced bus), there can be

 * only a single PxTLB broadcast at a time; this must be guaranteed

 * by software.  We put a spinlock around all TLB flushes  to

 * ensure this.

 */

DEFINE_SPINLOCK(pa_tlb_lock);

EXPORT_SYMBOL(pa_tlb_lock);

#endif



struct pdc_cache_info cache_info __read_mostly;

#ifndef CONFIG_PA20
@@ -91,7 +88,8 @@ update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) 


		flush_kernel_dcache_page(page);

		clear_bit(PG_dcache_dirty, &page->flags);

	}

	} else if (parisc_requires_coherency())

		flush_kernel_dcache_page(page);

}



void
@@ -370,3 +368,45 @@ void parisc_setup_cache_timing(void) 


	printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());

}



extern void purge_kernel_dcache_page(unsigned long);

extern void clear_user_page_asm(void *page, unsigned long vaddr);



void clear_user_page(void *page, unsigned long vaddr, struct page *pg)

{

	purge_kernel_dcache_page((unsigned long)page);

	purge_tlb_start();

	pdtlb_kernel(page);

	purge_tlb_end();

	clear_user_page_asm(page, vaddr);

}

EXPORT_SYMBOL(clear_user_page);



void flush_kernel_dcache_page_addr(void *addr)

{

	flush_kernel_dcache_page_asm(addr);

	purge_tlb_start();

	pdtlb_kernel(addr);

	purge_tlb_end();

}

EXPORT_SYMBOL(flush_kernel_dcache_page_addr);



void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,

		    struct page *pg)

{

	/* no coherency needed (all in kmap/kunmap) */

	copy_user_page_asm(vto, vfrom);

	if (!parisc_requires_coherency())

		flush_kernel_dcache_page_asm(vto);

}

EXPORT_SYMBOL(copy_user_page);



#ifdef CONFIG_PA8X00



void kunmap_parisc(void *addr)

{

	if (parisc_requires_coherency())

		flush_kernel_dcache_page_addr(addr);

}

EXPORT_SYMBOL(kunmap_parisc);

#endif

arch/parisc/kernel/entry.S

+5 −16
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 




#include <asm/psw.h>

#include <asm/cache.h>		/* for L1_CACHE_SHIFT */

#include <asm/assembly.h>	/* for LDREG/STREG defines */

#include <asm/pgtable.h>

#include <asm/signal.h>
@@ -478,11 +479,7 @@ 
	bb,>=,n		\pmd,_PxD_PRESENT_BIT,\fault

	DEP		%r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */

	copy		\pmd,%r9

#ifdef CONFIG_64BIT

	shld		%r9,PxD_VALUE_SHIFT,\pmd

#else

	shlw		%r9,PxD_VALUE_SHIFT,\pmd

#endif

	SHLREG		%r9,PxD_VALUE_SHIFT,\pmd

	EXTR		\va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index

	DEP		%r0,31,PAGE_SHIFT,\pmd  /* clear offset */

	shladd		\index,BITS_PER_PTE_ENTRY,\pmd,\pmd
@@ -970,11 +967,7 @@ intr_return: 
	/* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) amount

	** irq_stat[] is defined using ____cacheline_aligned.

	*/

#ifdef CONFIG_64BIT

	shld	%r1, 6, %r20

#else

	shlw	%r1, 5, %r20

#endif

	SHLREG	%r1,L1_CACHE_SHIFT,%r20

	add     %r19,%r20,%r19	/* now have &irq_stat[smp_processor_id()] */

#endif /* CONFIG_SMP */
@@ -1076,7 +1069,7 @@ intr_do_preempt: 
	BL	preempt_schedule_irq, %r2

	nop



	b	intr_restore		/* ssm PSW_SM_I done by intr_restore */

	b,n	intr_restore		/* ssm PSW_SM_I done by intr_restore */

#endif /* CONFIG_PREEMPT */



	.import do_signal,code
@@ -2115,11 +2108,7 @@ syscall_check_bh: 
	ldw     TI_CPU-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26 /* cpu # */



	/* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) bits */

#ifdef CONFIG_64BIT

	shld	%r26, 6, %r20

#else

	shlw	%r26, 5, %r20

#endif

	SHLREG	%r26,L1_CACHE_SHIFT,%r20

	add     %r19,%r20,%r19	/* now have &irq_stat[smp_processor_id()] */

#endif /* CONFIG_SMP */

CRA Git | Maintained and supported by SUSTech CRA and CCSE