Commit 5a85a642 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v5.4-2' of https://github.com/BayLibre/clk-meson into clk-meson 

Pull second set of Amlogic clk driver updates from Jerome Brunet:

 - Add g12a reset support to the axg audio clock controller
 - Add sm1 support to the g12a clock controller

* tag 'clk-meson-v5.4-2' of https://github.com/BayLibre/clk-meson:
  clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
  clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
  clk: meson: g12a: add support for SM1 GP1 PLL
  dt-bindings: clk: meson: add sm1 periph clock controller bindings
  clk: meson: axg-audio: add g12a reset support
  dt-bindings: clock: meson: add resets to the audio clock controller
parents 7c9dc000 da3ceae4

Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ Required Properties: 
				       components.

- resets	: phandle of the internal reset line

- #clock-cells	: should be 1.

- #reset-cells  : should be 1 on the g12a (and following) soc family



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt

+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ Required Properties: 
		"amlogic,axg-clkc" for AXG SoC.

		"amlogic,g12a-clkc" for G12A SoC.

		"amlogic,g12b-clkc" for G12B SoC.

		"amlogic,sm1-clkc" for SM1 SoC.

- clocks : list of clock phandle, one for each entry clock-names.

- clock-names : should contain the following:

  * "xtal": the platform xtal

drivers/clk/meson/axg-audio.c

+105 −2
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/platform_device.h>

#include <linux/regmap.h>

#include <linux/reset.h>

#include <linux/reset-controller.h>

#include <linux/slab.h>



#include "axg-audio.h"
@@ -918,6 +919,84 @@ static int devm_clk_get_enable(struct device *dev, char *id) 
	return 0;

}



struct axg_audio_reset_data {

	struct reset_controller_dev rstc;

	struct regmap *map;

	unsigned int offset;

};



static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,

					unsigned long id,

					unsigned int *reg,

					unsigned int *bit)

{

	unsigned int stride = regmap_get_reg_stride(rst->map);



	*reg = (id / (stride * BITS_PER_BYTE)) * stride;

	*reg += rst->offset;

	*bit = id % (stride * BITS_PER_BYTE);

}



static int axg_audio_reset_update(struct reset_controller_dev *rcdev,

				unsigned long id, bool assert)

{

	struct axg_audio_reset_data *rst =

		container_of(rcdev, struct axg_audio_reset_data, rstc);

	unsigned int offset, bit;



	axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);



	regmap_update_bits(rst->map, offset, BIT(bit),

			assert ? BIT(bit) : 0);



	return 0;

}



static int axg_audio_reset_status(struct reset_controller_dev *rcdev,

				unsigned long id)

{

	struct axg_audio_reset_data *rst =

		container_of(rcdev, struct axg_audio_reset_data, rstc);

	unsigned int val, offset, bit;



	axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);



	regmap_read(rst->map, offset, &val);



	return !!(val & BIT(bit));

}



static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,

				unsigned long id)

{

	return axg_audio_reset_update(rcdev, id, true);

}



static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,

				unsigned long id)

{

	return axg_audio_reset_update(rcdev, id, false);

}



static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,

				unsigned long id)

{

	int ret;



	ret = axg_audio_reset_assert(rcdev, id);

	if (ret)

		return ret;



	return axg_audio_reset_deassert(rcdev, id);

}



static const struct reset_control_ops axg_audio_rstc_ops = {

	.assert = axg_audio_reset_assert,

	.deassert = axg_audio_reset_deassert,

	.reset = axg_audio_reset_toggle,

	.status = axg_audio_reset_status,

};



static const struct regmap_config axg_audio_regmap_cfg = {

	.reg_bits	= 32,

	.val_bits	= 32,
@@ -927,12 +1006,15 @@ static const struct regmap_config axg_audio_regmap_cfg = { 


struct audioclk_data {

	struct clk_hw_onecell_data *hw_onecell_data;

	unsigned int reset_offset;

	unsigned int reset_num;

};



static int axg_audio_clkc_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	const struct audioclk_data *data;

	struct axg_audio_reset_data *rst;

	struct regmap *map;

	struct resource *res;

	void __iomem *regs;
@@ -984,8 +1066,27 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) 
		}

	}



	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,

	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,

					data->hw_onecell_data);

	if (ret)

		return ret;



	/* Stop here if there is no reset */

	if (!data->reset_num)

		return 0;



	rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);

	if (!rst)

		return -ENOMEM;



	rst->map = map;

	rst->offset = data->reset_offset;

	rst->rstc.nr_resets = data->reset_num;

	rst->rstc.ops = &axg_audio_rstc_ops;

	rst->rstc.of_node = dev->of_node;

	rst->rstc.owner = THIS_MODULE;



	return devm_reset_controller_register(dev, &rst->rstc);

}



static const struct audioclk_data axg_audioclk_data = {
@@ -994,6 +1095,8 @@ static const struct audioclk_data axg_audioclk_data = { 


static const struct audioclk_data g12a_audioclk_data = {

	.hw_onecell_data = &g12a_audio_hw_onecell_data,

	.reset_offset = AUDIO_SW_RESET,

	.reset_num = 26,

};



static const struct of_device_id clkc_match_table[] = {

drivers/clk/meson/axg-audio.h

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#define AUDIO_MCLK_F_CTRL	0x018

#define AUDIO_MST_PAD_CTRL0	0x01c

#define AUDIO_MST_PAD_CTRL1	0x020

#define AUDIO_SW_RESET		0x024

#define AUDIO_MST_A_SCLK_CTRL0	0x040

#define AUDIO_MST_A_SCLK_CTRL1	0x044

#define AUDIO_MST_B_SCLK_CTRL0	0x048

drivers/clk/meson/g12a.c

+544 −0
Original line number Diff line number Diff line
@@ -676,6 +676,226 @@ static struct clk_regmap g12b_cpub_clk = { 
	},

};



static struct clk_regmap sm1_gp1_pll;



/* Datasheet names this field as "premux0" */

static struct clk_regmap sm1_dsu_clk_premux0 = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL5,

		.mask = 0x3,

		.shift = 0,

	},

	.hw.init = &(struct clk_init_data){

		.name = "dsu_clk_dyn0_sel",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_data = (const struct clk_parent_data []) {

			{ .fw_name = "xtal", },

			{ .hw = &g12a_fclk_div2.hw },

			{ .hw = &g12a_fclk_div3.hw },

			{ .hw = &sm1_gp1_pll.hw },

		},

		.num_parents = 4,

	},

};



/* Datasheet names this field as "premux1" */

static struct clk_regmap sm1_dsu_clk_premux1 = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL5,

		.mask = 0x3,

		.shift = 16,

	},

	.hw.init = &(struct clk_init_data){

		.name = "dsu_clk_dyn1_sel",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_data = (const struct clk_parent_data []) {

			{ .fw_name = "xtal", },

			{ .hw = &g12a_fclk_div2.hw },

			{ .hw = &g12a_fclk_div3.hw },

			{ .hw = &sm1_gp1_pll.hw },

		},

		.num_parents = 4,

	},

};



/* Datasheet names this field as "Mux0_divn_tcnt" */

static struct clk_regmap sm1_dsu_clk_mux0_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_SYS_CPU_CLK_CNTL5,

		.shift = 4,

		.width = 6,

	},

	.hw.init = &(struct clk_init_data){

		.name = "dsu_clk_dyn0_div",

		.ops = &clk_regmap_divider_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&sm1_dsu_clk_premux0.hw

		},

		.num_parents = 1,

	},

};



/* Datasheet names this field as "postmux0" */

static struct clk_regmap sm1_dsu_clk_postmux0 = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL5,

		.mask = 0x1,

		.shift = 2,

	},

	.hw.init = &(struct clk_init_data){

		.name = "dsu_clk_dyn0",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&sm1_dsu_clk_premux0.hw,

			&sm1_dsu_clk_mux0_div.hw,

		},

		.num_parents = 2,

	},

};



/* Datasheet names this field as "Mux1_divn_tcnt" */

static struct clk_regmap sm1_dsu_clk_mux1_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_SYS_CPU_CLK_CNTL5,

		.shift = 20,

		.width = 6,

	},

	.hw.init = &(struct clk_init_data){

		.name = "dsu_clk_dyn1_div",

		.ops = &clk_regmap_divider_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&sm1_dsu_clk_premux1.hw

		},

		.num_parents = 1,

	},

};



/* Datasheet names this field as "postmux1" */

static struct clk_regmap sm1_dsu_clk_postmux1 = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL5,

		.mask = 0x1,

		.shift = 18,

	},

	.hw.init = &(struct clk_init_data){

		.name = "dsu_clk_dyn1",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&sm1_dsu_clk_premux1.hw,

			&sm1_dsu_clk_mux1_div.hw,

		},

		.num_parents = 2,

	},

};



/* Datasheet names this field as "Final_dyn_mux_sel" */

static struct clk_regmap sm1_dsu_clk_dyn = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL5,

		.mask = 0x1,

		.shift = 10,

	},

	.hw.init = &(struct clk_init_data){

		.name = "dsu_clk_dyn",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&sm1_dsu_clk_postmux0.hw,

			&sm1_dsu_clk_postmux1.hw,

		},

		.num_parents = 2,

	},

};



/* Datasheet names this field as "Final_mux_sel" */

static struct clk_regmap sm1_dsu_final_clk = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL5,

		.mask = 0x1,

		.shift = 11,

	},

	.hw.init = &(struct clk_init_data){

		.name = "dsu_clk_final",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&sm1_dsu_clk_dyn.hw,

			&g12a_sys_pll.hw,

		},

		.num_parents = 2,

	},

};



/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */

static struct clk_regmap sm1_cpu1_clk = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL6,

		.mask = 0x1,

		.shift = 24,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu1_clk",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_cpu_clk.hw,

			/* This CPU also have a dedicated clock tree */

		},

		.num_parents = 1,

	},

};



/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */

static struct clk_regmap sm1_cpu2_clk = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL6,

		.mask = 0x1,

		.shift = 25,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu2_clk",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_cpu_clk.hw,

			/* This CPU also have a dedicated clock tree */

		},

		.num_parents = 1,

	},

};



/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */

static struct clk_regmap sm1_cpu3_clk = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL6,

		.mask = 0x1,

		.shift = 26,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu3_clk",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_cpu_clk.hw,

			/* This CPU also have a dedicated clock tree */

		},

		.num_parents = 1,

	},

};



/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */

static struct clk_regmap sm1_dsu_clk = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL6,

		.mask = 0x1,

		.shift = 27,

	},

	.hw.init = &(struct clk_init_data){

		.name = "dsu_clk",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_cpu_clk.hw,

			&sm1_dsu_final_clk.hw,

		},

		.num_parents = 2,

	},

};



static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,

					unsigned long event, void *data)

{
@@ -1443,6 +1663,69 @@ static struct clk_regmap g12a_gp0_pll = { 
	},

};



static struct clk_regmap sm1_gp1_pll_dco = {

	.data = &(struct meson_clk_pll_data){

		.en = {

			.reg_off = HHI_GP1_PLL_CNTL0,

			.shift   = 28,

			.width   = 1,

		},

		.m = {

			.reg_off = HHI_GP1_PLL_CNTL0,

			.shift   = 0,

			.width   = 8,

		},

		.n = {

			.reg_off = HHI_GP1_PLL_CNTL0,

			.shift   = 10,

			.width   = 5,

		},

		.frac = {

			.reg_off = HHI_GP1_PLL_CNTL1,

			.shift   = 0,

			.width   = 17,

		},

		.l = {

			.reg_off = HHI_GP1_PLL_CNTL0,

			.shift   = 31,

			.width   = 1,

		},

		.rst = {

			.reg_off = HHI_GP1_PLL_CNTL0,

			.shift   = 29,

			.width   = 1,

		},

	},

	.hw.init = &(struct clk_init_data){

		.name = "gp1_pll_dco",

		.ops = &meson_clk_pll_ro_ops,

		.parent_data = &(const struct clk_parent_data) {

			.fw_name = "xtal",

		},

		.num_parents = 1,

		/* This clock feeds the DSU, avoid disabling it */

		.flags = CLK_IS_CRITICAL,

	},

};



static struct clk_regmap sm1_gp1_pll = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_GP1_PLL_CNTL0,

		.shift = 16,

		.width = 3,

		.flags = (CLK_DIVIDER_POWER_OF_TWO |

			  CLK_DIVIDER_ROUND_CLOSEST),

	},

	.hw.init = &(struct clk_init_data){

		.name = "gp1_pll",

		.ops = &clk_regmap_divider_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&sm1_gp1_pll_dco.hw

		},

		.num_parents = 1,

	},

};



/*

 * Internal hifi pll emulation configuration parameters

 */
@@ -4121,6 +4404,240 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { 
	.num = NR_CLKS,

};



static struct clk_hw_onecell_data sm1_hw_onecell_data = {

	.hws = {

		[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,

		[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,

		[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,

		[CLKID_FCLK_DIV3]		= &g12a_fclk_div3.hw,

		[CLKID_FCLK_DIV4]		= &g12a_fclk_div4.hw,

		[CLKID_FCLK_DIV5]		= &g12a_fclk_div5.hw,

		[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,

		[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,

		[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,

		[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,

		[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,

		[CLKID_CLK81]			= &g12a_clk81.hw,

		[CLKID_MPLL0]			= &g12a_mpll0.hw,

		[CLKID_MPLL1]			= &g12a_mpll1.hw,

		[CLKID_MPLL2]			= &g12a_mpll2.hw,

		[CLKID_MPLL3]			= &g12a_mpll3.hw,

		[CLKID_DDR]			= &g12a_ddr.hw,

		[CLKID_DOS]			= &g12a_dos.hw,

		[CLKID_AUDIO_LOCKER]		= &g12a_audio_locker.hw,

		[CLKID_MIPI_DSI_HOST]		= &g12a_mipi_dsi_host.hw,

		[CLKID_ETH_PHY]			= &g12a_eth_phy.hw,

		[CLKID_ISA]			= &g12a_isa.hw,

		[CLKID_PL301]			= &g12a_pl301.hw,

		[CLKID_PERIPHS]			= &g12a_periphs.hw,

		[CLKID_SPICC0]			= &g12a_spicc_0.hw,

		[CLKID_I2C]			= &g12a_i2c.hw,

		[CLKID_SANA]			= &g12a_sana.hw,

		[CLKID_SD]			= &g12a_sd.hw,

		[CLKID_RNG0]			= &g12a_rng0.hw,

		[CLKID_UART0]			= &g12a_uart0.hw,

		[CLKID_SPICC1]			= &g12a_spicc_1.hw,

		[CLKID_HIU_IFACE]		= &g12a_hiu_reg.hw,

		[CLKID_MIPI_DSI_PHY]		= &g12a_mipi_dsi_phy.hw,

		[CLKID_ASSIST_MISC]		= &g12a_assist_misc.hw,

		[CLKID_SD_EMMC_A]		= &g12a_emmc_a.hw,

		[CLKID_SD_EMMC_B]		= &g12a_emmc_b.hw,

		[CLKID_SD_EMMC_C]		= &g12a_emmc_c.hw,

		[CLKID_AUDIO_CODEC]		= &g12a_audio_codec.hw,

		[CLKID_AUDIO]			= &g12a_audio.hw,

		[CLKID_ETH]			= &g12a_eth_core.hw,

		[CLKID_DEMUX]			= &g12a_demux.hw,

		[CLKID_AUDIO_IFIFO]		= &g12a_audio_ififo.hw,

		[CLKID_ADC]			= &g12a_adc.hw,

		[CLKID_UART1]			= &g12a_uart1.hw,

		[CLKID_G2D]			= &g12a_g2d.hw,

		[CLKID_RESET]			= &g12a_reset.hw,

		[CLKID_PCIE_COMB]		= &g12a_pcie_comb.hw,

		[CLKID_PARSER]			= &g12a_parser.hw,

		[CLKID_USB]			= &g12a_usb_general.hw,

		[CLKID_PCIE_PHY]		= &g12a_pcie_phy.hw,

		[CLKID_AHB_ARB0]		= &g12a_ahb_arb0.hw,

		[CLKID_AHB_DATA_BUS]		= &g12a_ahb_data_bus.hw,

		[CLKID_AHB_CTRL_BUS]		= &g12a_ahb_ctrl_bus.hw,

		[CLKID_HTX_HDCP22]		= &g12a_htx_hdcp22.hw,

		[CLKID_HTX_PCLK]		= &g12a_htx_pclk.hw,

		[CLKID_BT656]			= &g12a_bt656.hw,

		[CLKID_USB1_DDR_BRIDGE]		= &g12a_usb1_to_ddr.hw,

		[CLKID_MMC_PCLK]		= &g12a_mmc_pclk.hw,

		[CLKID_UART2]			= &g12a_uart2.hw,

		[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,

		[CLKID_GIC]			= &g12a_gic.hw,

		[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,

		[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,

		[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,

		[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,

		[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,

		[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,

		[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,

		[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,

		[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,

		[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,

		[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,

		[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,

		[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,

		[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,

		[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,

		[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,

		[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,

		[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,

		[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,

		[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,

		[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,

		[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,

		[CLKID_VCLK2_VENCP0]		= &g12a_vclk2_vencp0.hw,

		[CLKID_VCLK2_VENCP1]		= &g12a_vclk2_vencp1.hw,

		[CLKID_VCLK2_VENCT0]		= &g12a_vclk2_venct0.hw,

		[CLKID_VCLK2_VENCT1]		= &g12a_vclk2_venct1.hw,

		[CLKID_VCLK2_OTHER]		= &g12a_vclk2_other.hw,

		[CLKID_VCLK2_ENCI]		= &g12a_vclk2_enci.hw,

		[CLKID_VCLK2_ENCP]		= &g12a_vclk2_encp.hw,

		[CLKID_DAC_CLK]			= &g12a_dac_clk.hw,

		[CLKID_AOCLK]			= &g12a_aoclk_gate.hw,

		[CLKID_IEC958]			= &g12a_iec958_gate.hw,

		[CLKID_ENC480P]			= &g12a_enc480p.hw,

		[CLKID_RNG1]			= &g12a_rng1.hw,

		[CLKID_VCLK2_ENCT]		= &g12a_vclk2_enct.hw,

		[CLKID_VCLK2_ENCL]		= &g12a_vclk2_encl.hw,

		[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,

		[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,

		[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,

		[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,

		[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,

		[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,

		[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,

		[CLKID_DMA]			= &g12a_dma.hw,

		[CLKID_EFUSE]			= &g12a_efuse.hw,

		[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,

		[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,

		[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,

		[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,

		[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,

		[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,

		[CLKID_VPU_0]			= &g12a_vpu_0.hw,

		[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,

		[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,

		[CLKID_VPU_1]			= &g12a_vpu_1.hw,

		[CLKID_VPU]			= &g12a_vpu.hw,

		[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,

		[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,

		[CLKID_VAPB_0]			= &g12a_vapb_0.hw,

		[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,

		[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,

		[CLKID_VAPB_1]			= &g12a_vapb_1.hw,

		[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,

		[CLKID_VAPB]			= &g12a_vapb.hw,

		[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,

		[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,

		[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,

		[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,

		[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,

		[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,

		[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,

		[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,

		[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,

		[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,

		[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,

		[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,

		[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,

		[CLKID_VCLK]			= &g12a_vclk.hw,

		[CLKID_VCLK2]			= &g12a_vclk2.hw,

		[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,

		[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,

		[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,

		[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,

		[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,

		[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,

		[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,

		[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,

		[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,

		[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,

		[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,

		[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,

		[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,

		[CLKID_VCLK_DIV12]		= &g12a_vclk_div12.hw,

		[CLKID_VCLK2_DIV2]		= &g12a_vclk2_div2.hw,

		[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,

		[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,

		[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,

		[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,

		[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,

		[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,

		[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,

		[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,

		[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,

		[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,

		[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,

		[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,

		[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,

		[CLKID_HDMI]			= &g12a_hdmi.hw,

		[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,

		[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,

		[CLKID_MALI_0]			= &g12a_mali_0.hw,

		[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,

		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,

		[CLKID_MALI_1]			= &g12a_mali_1.hw,

		[CLKID_MALI]			= &g12a_mali.hw,

		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,

		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,

		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,

		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,

		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,

		[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,

		[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,

		[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,

		[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,

		[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,

		[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,

		[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,

		[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,

		[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,

		[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,

		[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,

		[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,

		[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,

		[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,

		[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,

		[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,

		[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,

		[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,

		[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,

		[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,

		[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,

		[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,

		[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,

		[CLKID_VDEC_1]			= &g12a_vdec_1.hw,

		[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,

		[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,

		[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,

		[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,

		[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,

		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,

		[CLKID_TS_DIV]			= &g12a_ts_div.hw,

		[CLKID_TS]			= &g12a_ts.hw,

		[CLKID_GP1_PLL_DCO]		= &sm1_gp1_pll_dco.hw,

		[CLKID_GP1_PLL]			= &sm1_gp1_pll.hw,

		[CLKID_DSU_CLK_DYN0_SEL]	= &sm1_dsu_clk_premux0.hw,

		[CLKID_DSU_CLK_DYN0_DIV]	= &sm1_dsu_clk_premux1.hw,

		[CLKID_DSU_CLK_DYN0]		= &sm1_dsu_clk_mux0_div.hw,

		[CLKID_DSU_CLK_DYN1_SEL]	= &sm1_dsu_clk_postmux0.hw,

		[CLKID_DSU_CLK_DYN1_DIV]	= &sm1_dsu_clk_mux1_div.hw,

		[CLKID_DSU_CLK_DYN1]		= &sm1_dsu_clk_postmux1.hw,

		[CLKID_DSU_CLK_DYN]		= &sm1_dsu_clk_dyn.hw,

		[CLKID_DSU_CLK_FINAL]		= &sm1_dsu_final_clk.hw,

		[CLKID_DSU_CLK]			= &sm1_dsu_clk.hw,

		[CLKID_CPU1_CLK]		= &sm1_cpu1_clk.hw,

		[CLKID_CPU2_CLK]		= &sm1_cpu2_clk.hw,

		[CLKID_CPU3_CLK]		= &sm1_cpu3_clk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,

};



/* Convenience table to populate regmap in .probe */

static struct clk_regmap *const g12a_clk_regmaps[] = {

	&g12a_clk81,
@@ -4336,6 +4853,20 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { 
	&g12b_cpub_clk_axi,

	&g12b_cpub_clk_trace_sel,

	&g12b_cpub_clk_trace,

	&sm1_gp1_pll_dco,

	&sm1_gp1_pll,

	&sm1_dsu_clk_premux0,

	&sm1_dsu_clk_premux1,

	&sm1_dsu_clk_mux0_div,

	&sm1_dsu_clk_postmux0,

	&sm1_dsu_clk_mux1_div,

	&sm1_dsu_clk_postmux1,

	&sm1_dsu_clk_dyn,

	&sm1_dsu_final_clk,

	&sm1_dsu_clk,

	&sm1_cpu1_clk,

	&sm1_cpu2_clk,

	&sm1_cpu3_clk,

};



static const struct reg_sequence g12a_init_regs[] = {
@@ -4532,6 +5063,15 @@ static const struct meson_g12a_data g12b_clkc_data = { 
	.dvfs_setup = meson_g12b_dvfs_setup,

};



static const struct meson_g12a_data sm1_clkc_data = {

	.eeclkc_data = {

		.regmap_clks = g12a_clk_regmaps,

		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),

		.hw_onecell_data = &sm1_hw_onecell_data,

	},

	.dvfs_setup = meson_g12a_dvfs_setup,

};



static const struct of_device_id clkc_match_table[] = {

	{

		.compatible = "amlogic,g12a-clkc",
@@ -4541,6 +5081,10 @@ static const struct of_device_id clkc_match_table[] = { 
		.compatible = "amlogic,g12b-clkc",

		.data = &g12b_clkc_data.eeclkc_data

	},

	{

		.compatible = "amlogic,sm1-clkc",

		.data = &sm1_clkc_data.eeclkc_data

	},

	{}

};

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