Commit da3ceae4 authored by Neil Armstrong's avatar Neil Armstrong Committed by Jerome Brunet
Browse files

clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks 



The Amlogic SM1 can set a dedicated clock frequency for each CPU core by
having a dedicate tree for each core similar to the CPU0 tree.
Like the DSU tree, a supplementaty mux has been added to use the CPU0
frequency instead.

But since the cluster only has a single power rail and shares a single PLL,
it's not worth adding 3 unsused clock tree, so we add only the mux to
select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores.

They are set read-only because the early boot stages sets them to select
the CPU0 input clock.

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 2edccd31

drivers/clk/meson/g12a.c

+60 −0
Original line number Diff line number Diff line
@@ -824,6 +824,60 @@ static struct clk_regmap sm1_dsu_final_clk = { 
	},

};



/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */

static struct clk_regmap sm1_cpu1_clk = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL6,

		.mask = 0x1,

		.shift = 24,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu1_clk",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_cpu_clk.hw,

			/* This CPU also have a dedicated clock tree */

		},

		.num_parents = 1,

	},

};



/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */

static struct clk_regmap sm1_cpu2_clk = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL6,

		.mask = 0x1,

		.shift = 25,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu2_clk",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_cpu_clk.hw,

			/* This CPU also have a dedicated clock tree */

		},

		.num_parents = 1,

	},

};



/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */

static struct clk_regmap sm1_cpu3_clk = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SYS_CPU_CLK_CNTL6,

		.mask = 0x1,

		.shift = 26,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu3_clk",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_cpu_clk.hw,

			/* This CPU also have a dedicated clock tree */

		},

		.num_parents = 1,

	},

};



/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */

static struct clk_regmap sm1_dsu_clk = {

	.data = &(struct clk_regmap_mux_data){
@@ -4576,6 +4630,9 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { 
		[CLKID_DSU_CLK_DYN]		= &sm1_dsu_clk_dyn.hw,

		[CLKID_DSU_CLK_FINAL]		= &sm1_dsu_final_clk.hw,

		[CLKID_DSU_CLK]			= &sm1_dsu_clk.hw,

		[CLKID_CPU1_CLK]		= &sm1_cpu1_clk.hw,

		[CLKID_CPU2_CLK]		= &sm1_cpu2_clk.hw,

		[CLKID_CPU3_CLK]		= &sm1_cpu3_clk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,
@@ -4807,6 +4864,9 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { 
	&sm1_dsu_clk_dyn,

	&sm1_dsu_final_clk,

	&sm1_dsu_clk,

	&sm1_cpu1_clk,

	&sm1_cpu2_clk,

	&sm1_cpu3_clk,

};



static const struct reg_sequence g12a_init_regs[] = {

drivers/clk/meson/g12a.h

+1 −1
Original line number Diff line number Diff line
@@ -256,7 +256,7 @@ 
#define CLKID_DSU_CLK_DYN			250

#define CLKID_DSU_CLK_FINAL			251



#define NR_CLKS					253

#define NR_CLKS					256



/* include the CLKIDs that have been made part of the DT binding */

#include <dt-bindings/clock/g12a-clkc.h>

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