Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp'...

domain binding[2].

Required properties:

- compatible:		Should be "fsl,scu-pd".

- #address-cells:	Should be 1.

- #size-cells:		Should be 0.

Required properties for power domain sub nodes:

- #power-domain-cells:	Must be 0.

Optional Properties:

- reg:			Resource ID of this power domain.

			No exist means uncontrollable by user.

- compatible:		Should be "fsl,imx8qxp-scu-pd".

- #power-domain-cells:	Must be 1. Contains the Resource ID used by

			SCU commands.

			See detailed Resource ID list from:

			include/dt-bindings/power/imx-rsrc.h

- power-domains:	phandle pointing to the parent power domain.

			include/dt-bindings/firmware/imx/rsrc.h

Clock bindings based on SCU Message Protocol

------------------------------------------------------------

			...

		};

		imx8qx-pm {

			compatible = "fsl,scu-pd";

			#address-cells = <1>;

			#size-cells = <0>;

			pd_dma: dma-power-domain {

				#power-domain-cells = <0>;

				pd_dma_lpuart0: dma-lpuart0@57 {

					reg = <SC_R_UART_0>;

					#power-domain-cells = <0>;

					power-domains = <&pd_dma>;

				};

				...

			};

			...

		pd: imx8qx-pd {

			compatible = "fsl,imx8qxp-scu-pd";

			#power-domain-cells = <1>;

		};

	};

};

	clocks = <&clk IMX8QXP_UART0_CLK>,

		 <&clk IMX8QXP_UART0_IPG_CLK>;

	clock-names = "per", "ipg";

	power-domains = <&pd_dma_lpuart0>;

	power-domains = <&pd IMX_SC_R_UART_0>;

};

  management IC (PMIC) triggered via PMIC_STBY_REQ signal.

  Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should

  be using "syscon-poweroff" driver instead.

- clocks: list of clock specifiers, must contain an entry for each entry

          in clock-names

- clock-names: valid names are "osc", "ckil", "ckih1", "anaclk1" and "anaclk2"

The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx6qdl-clock.h

* Clock bindings for Freescale i.MX7ULP

i.MX7ULP Clock functions are under joint control of the System

Clock Generation (SCG) modules, Peripheral Clock Control (PCC)

modules, and Core Mode Controller (CMC)1 blocks

The clocking scheme provides clear separation between M4 domain

and A7 domain. Except for a few clock sources shared between two

domains, such as the System Oscillator clock, the Slow IRC (SIRC),

and and the Fast IRC clock (FIRCLK), clock sources and clock

management are separated and contained within each domain.

M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.

A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.

Note: this binding doc is only for A7 clock domain.

System Clock Generation (SCG) modules:

---------------------------------------------------------------------

The System Clock Generation (SCG) is responsible for clock generation

and distribution across this device. Functions performed by the SCG

include: clock reference selection, generation of clock used to derive

processor, system, peripheral bus and external memory interface clocks,

source selection for peripheral clocks and control of power saving

clock gating mode.

Required properties:

- compatible:	Should be "fsl,imx7ulp-scg1".

- reg : 	Should contain registers location and length.

- #clock-cells:	Should be <1>.

- clocks:	Should contain the fixed input clocks.

- clock-names:  Should contain the following clock names:

		"rosc", "sosc", "sirc", "firc", "upll", "mpll".

Peripheral Clock Control (PCC) modules:

---------------------------------------------------------------------

The Peripheral Clock Control (PCC) is responsible for clock selection,

optional division and clock gating mode for peripherals in their

respected power domain

Required properties:

- compatible:	Should be one of:

		  "fsl,imx7ulp-pcc2",

		  "fsl,imx7ulp-pcc3".

- reg : 	Should contain registers location and length.

- #clock-cells:	Should be <1>.

- clocks:	Should contain the fixed input clocks.

- clock-names:  Should contain the following clock names:

		"nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2",

		"apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk",

		"mpll", "firc_bus_clk", "rosc", "spll_bus_clk";

The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.

See include/dt-bindings/clock/imx7ulp-clock.h

for the full list of i.MX7ULP clock IDs of each module.

Examples:

#include <dt-bindings/clock/imx7ulp-clock.h>

scg1: scg1@403e0000 {

	compatible = "fsl,imx7ulp-scg1;

	reg = <0x403e0000 0x10000>;

	clocks = <&rosc>, <&sosc>, <&sirc>,

		 <&firc>, <&upll>, <&mpll>;

	clock-names = "rosc", "sosc", "sirc",

		      "firc", "upll", "mpll";

	#clock-cells = <1>;

};

pcc2: pcc2@403f0000 {

	compatible = "fsl,imx7ulp-pcc2";

	reg = <0x403f0000 0x10000>;

	#clock-cells = <1>;

	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,

		 <&scg1 IMX7ULP_CLK_NIC1_DIV>,

		 <&scg1 IMX7ULP_CLK_DDR_DIV>,

		 <&scg1 IMX7ULP_CLK_APLL_PFD2>,

		 <&scg1 IMX7ULP_CLK_APLL_PFD1>,

		 <&scg1 IMX7ULP_CLK_APLL_PFD0>,

		 <&scg1 IMX7ULP_CLK_UPLL>,

		 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,

		 <&scg1 IMX7ULP_CLK_MIPI_PLL>,

		 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,

		 <&scg1 IMX7ULP_CLK_ROSC>,

		 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;

	clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",

		      "apll_pfd2", "apll_pfd1", "apll_pfd0",

		      "upll", "sosc_bus_clk", "mpll",

		      "firc_bus_clk", "rosc", "spll_bus_clk";

};

usdhc1: usdhc@40380000 {

	compatible = "fsl,imx7ulp-usdhc";

	reg = <0x40380000 0x10000>;

	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,

		 <&scg1 IMX7ULP_CLK_NIC1_DIV>,

		 <&pcc2 IMX7ULP_CLK_USDHC1>;

	clock-names ="ipg", "ahb", "per";

	bus-width = <4>;

};

* Clock bindings for NXP i.MX8M Quad

Required properties:

- compatible: Should be "fsl,imx8mq-ccm"

- reg: Address and length of the register set

- #clock-cells: Should be <1>

- clocks: list of clock specifiers, must contain an entry for each required

          entry in clock-names

- clock-names: should include the following entries:

    - "ckil"

    - "osc_25m"

    - "osc_27m"

    - "clk_ext1"

    - "clk_ext2"

    - "clk_ext3"

    - "clk_ext4"

The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx8mq-clock.h

for the full list of i.MX8M Quad clock IDs.

* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings

The Low-Power Clock Gate (LPCG) modules contain a local programming

model to control the clock gates for the peripherals. An LPCG module

is used to locally gate the clocks for the associated peripheral.

Note:

This level of clock gating is provided after the clocks are generated

by the SCU resources and clock controls. Thus even if the clock is

enabled by these control bits, it might still not be running based

on the base resource.

Required properties:

- compatible:	Should be one of:

		  "fsl,imx8qxp-lpcg-adma",

		  "fsl,imx8qxp-lpcg-conn",

		  "fsl,imx8qxp-lpcg-dc",

		  "fsl,imx8qxp-lpcg-dsp",

		  "fsl,imx8qxp-lpcg-gpu",

		  "fsl,imx8qxp-lpcg-hsio",

		  "fsl,imx8qxp-lpcg-img",

		  "fsl,imx8qxp-lpcg-lsio",

		  "fsl,imx8qxp-lpcg-vpu"

- reg:		Address and length of the register set

- #clock-cells:	Should be <1>

The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.

See the full list of clock IDs from:

include/dt-bindings/clock/imx8qxp-clock.h

Examples:

#include <dt-bindings/clock/imx8qxp-clock.h>

conn_lpcg: clock-controller@5b200000 {

	compatible = "fsl,imx8qxp-lpcg-conn";

	reg = <0x5b200000 0xb0000>;

	#clock-cells = <1>;

};

usdhc1: mmc@5b010000 {

	compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";

	interrupt-parent = <&gic>;

	interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;

	reg = <0x5b010000 0x10000>;

	clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>,

		 <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>,

		 <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>;

	clock-names = "ipg", "per", "ahb";

};