Commit 92991494 authored by Anson Huang's avatar Anson Huang Committed by Stephen Boyd
Browse files

clk: imx6q: add DCICx clocks gate 



On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks
gate in CCM_CCGR0 register, add them into clock tree for
clock management.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 0efcc2c0

drivers/clk/imx/clk-imx6q.c

+2 −0
Original line number Diff line number Diff line
@@ -737,6 +737,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
	clk[IMX6QDL_CLK_CAN1_SERIAL]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);

	clk[IMX6QDL_CLK_CAN2_IPG]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);

	clk[IMX6QDL_CLK_CAN2_SERIAL]  = imx_clk_gate2("can2_serial",   "can_root",          base + 0x68, 20);

	clk[IMX6QDL_CLK_DCIC1]        = imx_clk_gate2("dcic1",         "ipu1_podf",         base + 0x68, 24);

	clk[IMX6QDL_CLK_DCIC2]        = imx_clk_gate2("dcic2",         "ipu2_podf",         base + 0x68, 26);

	clk[IMX6QDL_CLK_ECSPI1]       = imx_clk_gate2("ecspi1",        "ecspi_root",        base + 0x6c, 0);

	clk[IMX6QDL_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);

	clk[IMX6QDL_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);

include/dt-bindings/clock/imx6qdl-clock.h

+3 −1
Original line number Diff line number Diff line
@@ -274,6 +274,8 @@ 
#define IMX6QDL_CLK_EPIT1			261

#define IMX6QDL_CLK_EPIT2			262

#define IMX6QDL_CLK_MMDC_P0_IPG			263

#define IMX6QDL_CLK_END				264

#define IMX6QDL_CLK_DCIC1			264

#define IMX6QDL_CLK_DCIC2			265

#define IMX6QDL_CLK_END				266



#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */

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