Merge tag 'nand/for-5.5' into mtd/next (589e1b6c) · Commits · 戴 / test

Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt

0 → 100644

+53 −0

Original line number	Diff line number	Diff line
		* Cadence NAND controller

		Required properties:
		- compatible : "cdns,hp-nfc"
		- reg : Contains two entries, each of which is a tuple consisting of a
		physical address and length. The first entry is the address and
		length of the controller register set. The second entry is the
		address and length of the Slave DMA data port.
		- reg-names: should contain "reg" and "sdma"
		- #address-cells: should be 1. The cell encodes the chip select connection.
		- #size-cells : should be 0.
		- interrupts : The interrupt number.
		- clocks: phandle of the controller core clock (nf_clk).

		Optional properties:
		- dmas: shall reference DMA channel associated to the NAND controller
		- cdns,board-delay-ps : Estimated Board delay. The value includes the total
		round trip delay for the signals and is used for deciding on values
		associated with data read capture. The example formula for SDR mode is
		the following:
		board delay = RE#PAD delay + PCB trace to device + PCB trace from device
		+ DQ PAD delay

		Child nodes represent the available NAND chips.

		Required properties of NAND chips:
		- reg: shall contain the native Chip Select ids from 0 to max supported by
		the cadence nand flash controller

		See Documentation/devicetree/bindings/mtd/nand.txt for more details on
		generic bindings.

		Example:

		nand_controller: nand-controller@60000000 {
		compatible = "cdns,hp-nfc";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
		reg-names = "reg", "sdma";
		clocks = <&nf_clk>;
		cdns,board-delay-ps = <4830>;
		interrupts = <2 0>;
		nand@0 {
		reg = <0>;
		label = "nand-1";
		};
		nand@1 {
		reg = <1>;
		label = "nand-2";
		};

		};

MAINTAINERS

+7 −0

Original line number	Diff line number	Diff line
		@@ -3594,6 +3594,13 @@ S: Maintained
		F: Documentation/devicetree/bindings/media/cdns,*.txt
		F: drivers/media/platform/cadence/cdns-csi2*

		CADENCE NAND DRIVER
		M: Piotr Sroka <piotrs@cadence.com>
		L: linux-mtd@lists.infradead.org
		S: Maintained
		F: drivers/mtd/nand/raw/cadence-nand-controller.c
		F: Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt

		CADET FM/AM RADIO RECEIVER DRIVER
		M: Hans Verkuil <hverkuil@xs4all.nl>
		L: linux-media@vger.kernel.org

drivers/mtd/nand/raw/Kconfig

+7 −0

Original line number	Diff line number	Diff line
		@@ -450,6 +450,13 @@ config MTD_NAND_PLATFORM
		devices. You will need to provide platform-specific functions
		via platform_data.

		config MTD_NAND_CADENCE
		tristate "Support Cadence NAND (HPNFC) controller"
		depends on OF \|\| COMPILE_TEST
		help
		Enable the driver for NAND flash on platforms using a Cadence NAND
		controller.

		comment "Misc"

		config MTD_SM_COMMON

drivers/mtd/nand/raw/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o
		obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
		obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o
		obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o
		obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o

		nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
		nand-objs += nand_onfi.o

drivers/mtd/nand/raw/brcmnand/brcmnand.c

+20 −3

Original line number	Diff line number	Diff line
		@@ -117,6 +117,18 @@ enum flash_dma_reg {
		FLASH_DMA_CURRENT_DESC_EXT,
		};

		/* flash_dma registers v0*/
		static const u16 flash_dma_regs_v0[] = {
		[FLASH_DMA_REVISION] = 0x00,
		[FLASH_DMA_FIRST_DESC] = 0x04,
		[FLASH_DMA_CTRL] = 0x08,
		[FLASH_DMA_MODE] = 0x0c,
		[FLASH_DMA_STATUS] = 0x10,
		[FLASH_DMA_INTERRUPT_DESC] = 0x14,
		[FLASH_DMA_ERROR_STATUS] = 0x18,
		[FLASH_DMA_CURRENT_DESC] = 0x1c,
		};

		/* flash_dma registers v1*/
		static const u16 flash_dma_regs_v1[] = {
		[FLASH_DMA_REVISION] = 0x00,
		@@ -597,6 +609,8 @@ static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl)
		/* flash_dma register offsets */
		if (ctrl->nand_version >= 0x0703)
		ctrl->flash_dma_offsets = flash_dma_regs_v4;
		else if (ctrl->nand_version == 0x0602)
		ctrl->flash_dma_offsets = flash_dma_regs_v0;
		else
		ctrl->flash_dma_offsets = flash_dma_regs_v1;
		}
		@@ -918,7 +932,7 @@ static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl)
		return;

		if (has_flash_dma(ctrl)) {
		ctrl->flash_dma_base = 0;
		ctrl->flash_dma_base = NULL;
		disable_irq(ctrl->dma_irq);
		}

		@@ -1673,8 +1687,11 @@ static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)

		flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
		(void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
		flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
		if (ctrl->nand_version > 0x0602) {
		flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT,
		upper_32_bits(desc));
		(void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
		}

		/* Start FLASH_DMA engine */
		ctrl->dma_pending = true;

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