Commit 575155a9 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
Browse files

drm/i915: add ValleyView specific force wake get/put functions 



ValleyView handles force wake differently than previous chipsets, so add
a couple of new functions for it.  But leave it disabled by default
until we test it (need a chip with the Punit enabled first).

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 64757876

drivers/gpu/drm/i915/i915_drv.c

+27 −1
Original line number Diff line number Diff line
@@ -465,6 +465,31 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 
	return ret;

}



void vlv_force_wake_get(struct drm_i915_private *dev_priv)

{

	int count;



	count = 0;



	/* Already awake? */

	if ((I915_READ(0x130094) & 0xa1) == 0xa1)

		return;



	I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);

	POSTING_READ(FORCEWAKE_VLV);



	count = 0;

	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)

		udelay(10);

}



void vlv_force_wake_put(struct drm_i915_private *dev_priv)

{

	I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);

	/* FIXME: confirm VLV behavior with Punit folks */

	POSTING_READ(FORCEWAKE_VLV);

}



static int i915_drm_freeze(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1007,7 +1032,8 @@ MODULE_LICENSE("GPL and additional rights"); 
#define NEEDS_FORCE_WAKE(dev_priv, reg) \

       (((dev_priv)->info->gen >= 6) && \

        ((reg) < 0x40000) &&            \

        ((reg) != FORCEWAKE))

        ((reg) != FORCEWAKE)) && \

       (!IS_VALLEYVIEW((dev_priv)->dev))



#define __i915_read(x, y) \

u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \

drivers/gpu/drm/i915/i915_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -1406,6 +1406,9 @@ extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); 
extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);

extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);



extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);

extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);



/* overlay */

#ifdef CONFIG_DEBUG_FS

extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -3820,6 +3820,8 @@ 
#define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)



#define  FORCEWAKE				0xA18C

#define  FORCEWAKE_VLV				0x1300b0

#define  FORCEWAKE_ACK_VLV			0x1300b4

#define  FORCEWAKE_ACK				0x130090

#define  FORCEWAKE_MT				0xa188 /* multi-threaded */

#define  FORCEWAKE_MT_ACK			0x130040

drivers/gpu/drm/i915/intel_display.c

+2 −0
Original line number Diff line number Diff line
@@ -9277,6 +9277,8 @@ static void intel_init_display(struct drm_device *dev) 
		dev_priv->display.update_wm = valleyview_update_wm;

		dev_priv->display.init_clock_gating =

			valleyview_init_clock_gating;

		dev_priv->display.force_wake_get = vlv_force_wake_get;

		dev_priv->display.force_wake_put = vlv_force_wake_put;

	} else if (IS_PINEVIEW(dev)) {

		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),

					    dev_priv->is_ddr3,

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