Commit 64757876 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
Browse files

agp/intel: add ValleyView AGP driver 



... and bind it right to the PCI id.

Note that there are still a few things to fix here:
- we need to move the tlb flush to a better place in drm/i915.
- we need to check snoop support on vlv and implement it.

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
[danvet: squash follow-on patch and add todo items to commit msg.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4b60d29e

drivers/char/agp/intel-agp.c

+1 −0
Original line number Diff line number Diff line
@@ -907,6 +907,7 @@ static struct pci_device_id agp_intel_pci_table[] = { 
	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),

	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),

	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),

	ID(PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB),

	{ }

};

drivers/char/agp/intel-agp.h

+3 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ 
#define G4x_GMCH_SIZE_VT_2M	(G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)



#define GFX_FLSH_CNTL		0x2170 /* 915+ */

#define GFX_FLSH_CNTL_VLV	0x101008



#define I810_DRAM_CTL		0x3000

#define I810_DRAM_ROW_0		0x00000001
@@ -234,6 +235,8 @@ 
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG		0x0166

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB		0x0158  /* Server */

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG		0x015A

#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB		0x0F00 /* VLV1 */

#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG		0x0F30



int intel_gmch_probe(struct pci_dev *pdev,

			       struct agp_bridge_data *bridge);

drivers/char/agp/intel-gtt.c

+25 −0
Original line number Diff line number Diff line
@@ -1179,6 +1179,20 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry, 
	writel(addr | pte_flags, intel_private.gtt + entry);

}



static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,

				   unsigned int flags)

{

	u32 pte_flags;



	pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;



	/* gen6 has bit11-4 for physical addr bit39-32 */

	addr |= (addr >> 28) & 0xff0;

	writel(addr | pte_flags, intel_private.gtt + entry);



	writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV);

}



static void gen6_cleanup(void)

{

}
@@ -1359,6 +1373,15 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = { 
	.check_flags = gen6_check_flags,

	.chipset_flush = i9xx_chipset_flush,

};

static const struct intel_gtt_driver valleyview_gtt_driver = {

	.gen = 7,

	.setup = i9xx_setup,

	.cleanup = gen6_cleanup,

	.write_entry = valleyview_write_entry,

	.dma_mask_size = 40,

	.check_flags = gen6_check_flags,

	.chipset_flush = i9xx_chipset_flush,

};



/* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of

 * driver and gmch_driver must be non-null, and find_gmch will determine
@@ -1463,6 +1486,8 @@ static const struct intel_gtt_driver_description { 
	    "Ivybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,

	    "Ivybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,

	    "ValleyView", &valleyview_gtt_driver },

	{ 0, NULL, NULL }

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE