Commit 57133a28 authored by Eric Yang's avatar Eric Yang Committed by Alex Deucher
Browse files

drm/amd/display: fix code to control 48mhz refclk 



[Why]
The SMU message to enable this feature looks at argument. Previous code
didn't send right argument. This change will allow the feature to be
be enabled.

[How]
Fixed one issue where SMU message to enable the feature was sent without
setting the parameter.

Signed-off-by: default avatarEric Yang <Eric.Yang2@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ab4a4072

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

+4 −3
Original line number Diff line number Diff line
@@ -649,8 +649,9 @@ void rn_clk_mgr_construct( 
			pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);

	}



	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {

		/* enable powerfeatures when displaycount goes to 0 */

	if (!debug->disable_48mhz_pwrdwn)

		rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr);

		rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);

	}

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

+2 −2
Original line number Diff line number Diff line
@@ -190,12 +190,12 @@ void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum 
		disp_count);

}



void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr)

void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

{

	rn_vbios_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown,

			0);

			enable);

}



void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int 
void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);

int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);

void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr);

void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);



#endif /* DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_ */

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -804,7 +804,7 @@ static const struct dc_debug_options debug_defaults_drv = { 
		.disable_pplib_wm_range = false,

		.scl_reset_length10 = true,

		.sanity_checks = true,

		.disable_48mhz_pwrdwn = true,

		.disable_48mhz_pwrdwn = false,

};



static const struct dc_debug_options debug_defaults_diags = {

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