Commit ab4a4072 authored by Eric Yang's avatar Eric Yang Committed by Alex Deucher
Browse files

drm/amd/display: exit PSR during detection 



[Why]
If 48mhz refclk is turned off during PSR, we will have issue doing
link training during detection.

[How]
Get out of PSR before detection

Signed-off-by: default avatarEric Yang <Eric.Yang2@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent edb922b0

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

+25 −0
Original line number Diff line number Diff line
@@ -65,6 +65,31 @@ int clk_mgr_helper_get_active_display_cnt( 
	return display_count;

}



void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)

{

	struct dc_link *edp_link = get_edp_link(dc);



	if (dc->hwss.exit_optimized_pwr_state)

		dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);



	if (edp_link) {

		clk_mgr->psr_allow_active_cache = edp_link->psr_allow_active;

		dc_link_set_psr_allow_active(edp_link, false, false);

	}



}



void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)

{

	struct dc_link *edp_link = get_edp_link(dc);



	if (edp_link)

		dc_link_set_psr_allow_active(edp_link, clk_mgr->psr_allow_active_cache, false);



	if (dc->hwss.optimize_pwr_state)

		dc->hwss.optimize_pwr_state(dc, dc->current_state);



}



struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)

{

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+11 −8
Original line number Diff line number Diff line
@@ -1074,15 +1074,14 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) 
{

	const struct dc *dc = link->dc;

	bool ret;

	/* get out of low power state */



	if (dc->hwss.exit_optimized_pwr_state)

		dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);

	/* get out of low power state */

	clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);



	ret = dc_link_detect_helper(link, reason);



	if (dc->hwss.optimize_pwr_state)

		dc->hwss.optimize_pwr_state(dc, dc->current_state);

	/* Go back to power optimized state */

	clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);



	return ret;

}
@@ -2421,13 +2420,17 @@ bool dc_link_set_abm_disable(const struct dc_link *link) 
	return true;

}



bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)

bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait)

{

	struct dc  *core_dc = link->ctx->dc;

	struct dmcu *dmcu = core_dc->res_pool->dmcu;



	if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_enabled)

		dmcu->funcs->set_psr_enable(dmcu, enable, wait);





	if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_feature_enabled)

		dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);



	link->psr_allow_active = allow_active;



	return true;

}

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+4 −4
Original line number Diff line number Diff line
@@ -2076,11 +2076,11 @@ static bool allow_hpd_rx_irq(const struct dc_link *link) 
	return false;

}



static bool handle_hpd_irq_psr_sink(const struct dc_link *link)

static bool handle_hpd_irq_psr_sink(struct dc_link *link)

{

	union dpcd_psr_configuration psr_configuration;



	if (!link->psr_enabled)

	if (!link->psr_feature_enabled)

		return false;



	dm_helpers_dp_read_dpcd(
@@ -2119,8 +2119,8 @@ static bool handle_hpd_irq_psr_sink(const struct dc_link *link) 
				sizeof(psr_error_status.raw));



			/* PSR error, disable and re-enable PSR */

			dc_link_set_psr_enable(link, false, true);

			dc_link_set_psr_enable(link, true, true);

			dc_link_set_psr_allow_active(link, false, true);

			dc_link_set_psr_allow_active(link, true, true);



			return true;

		} else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==

drivers/gpu/drm/amd/display/dc/dc_link.h

+15 −2
Original line number Diff line number Diff line
@@ -126,7 +126,8 @@ struct dc_link { 
	unsigned short chip_caps;

	unsigned int dpcd_sink_count;

	enum edp_revision edp_revision;

	bool psr_enabled;

	bool psr_feature_enabled;

	bool psr_allow_active;



	/* MST record stream using this link */

	struct link_flags {
@@ -158,6 +159,18 @@ static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_ 
	return dc->links[link_index];

}



static inline struct dc_link *get_edp_link(const struct dc *dc)

{

	int i;



	// report any eDP links, even unconnected DDI's

	for (i = 0; i < dc->link_count; i++) {

		if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)

			return dc->links[i];

	}

	return NULL;

}



/* Set backlight level of an embedded panel (eDP, LVDS).

 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer

 * and 16 bit fractional, where 1.0 is max backlight value.
@@ -170,7 +183,7 @@ int dc_link_get_backlight_level(const struct dc_link *dc_link); 


bool dc_link_set_abm_disable(const struct dc_link *dc_link);



bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait);

bool dc_link_set_psr_allow_active(struct dc_link *dc_link, bool enable, bool wait);



bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+2 −14
Original line number Diff line number Diff line
@@ -1410,7 +1410,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( 


	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;



	pipe_ctx->stream->link->psr_enabled = false;

	pipe_ctx->stream->link->psr_feature_enabled = false;



	return DC_OK;

}
@@ -1521,18 +1521,6 @@ static struct dc_stream_state *get_edp_stream(struct dc_state *context) 
	return NULL;

}



static struct dc_link *get_edp_link(struct dc *dc)

{

	int i;



	// report any eDP links, even unconnected DDI's

	for (i = 0; i < dc->link_count; i++) {

		if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)

			return dc->links[i];

	}

	return NULL;

}



static struct dc_link *get_edp_link_with_sink(

		struct dc *dc,

		struct dc_state *context)
@@ -1826,7 +1814,7 @@ static bool should_enable_fbc(struct dc *dc, 
		return false;



	/* PSR should not be enabled */

	if (pipe_ctx->stream->link->psr_enabled)

	if (pipe_ctx->stream->link->psr_feature_enabled)

		return false;



	/* Nothing to compress */

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