Commit 5622b2d6 authored by David Galiffi's avatar David Galiffi Committed by Alex Deucher
Browse files

drm/amd/display: Create debug option to disable v.active clock change policy. 



[WHY]
It has been a useful option in debugging GFXOFF and P.State Change issues.
May be required as for platform specific workaround.

[HOW]
Create option in enum dc_debug_options, "disable_vactive_clock_change".
When it is set, dm_dram_clock_change_vactive, will translate into
p_state_change_support: false.

Signed-off-by: default avatarDavid Galiffi <David.Galiffi@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5ed78cd6

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -423,6 +423,7 @@ struct dc_debug_options { 
	int force_clock_mode;/*every mode change.*/



	bool nv12_iflip_vm_wa;

	bool disable_dram_clock_change_vactive_support;

};



struct dc_debug_data {

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -2850,6 +2850,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 
	bool full_pstate_supported = false;

	bool dummy_pstate_supported = false;

	double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;

	context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = dc->debug.disable_dram_clock_change_vactive_support;



	if (fast_validate)

		return dcn20_validate_bandwidth_internal(dc, context, true);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

+2 −1
Original line number Diff line number Diff line
@@ -2577,7 +2577,8 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer 
			mode_lib->vba.MinActiveDRAMClockChangeMargin

					+ mode_lib->vba.DRAMClockChangeLatency;



	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {

	if (mode_lib->vba.DRAMClockChangeSupportsVActive &&

			mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {

		mode_lib->vba.DRAMClockChangeWatermark += 25;

		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;

	} else {

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

+3 −3
Original line number Diff line number Diff line
@@ -2611,8 +2611,8 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP 
			mode_lib->vba.MinActiveDRAMClockChangeMargin

					+ mode_lib->vba.DRAMClockChangeLatency;





	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {

	if (mode_lib->vba.DRAMClockChangeSupportsVActive &&

		mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {

		mode_lib->vba.DRAMClockChangeWatermark += 25;

		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;

	} else if (mode_lib->vba.DummyPStateCheck &&

drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

+1 −0
Original line number Diff line number Diff line
@@ -112,6 +112,7 @@ struct _vcs_dpi_soc_bounding_box_st { 
	bool do_urgent_latency_adjustment;

	double urgent_latency_adjustment_fabric_clock_component_us;

	double urgent_latency_adjustment_fabric_clock_reference_mhz;

	bool disable_dram_clock_change_vactive_support;

};



struct _vcs_dpi_ip_params_st {

CRA Git | Maintained and supported by SUSTech CRA and CCSE