Commit 5ed78cd6 authored by Anthony Koo's avatar Anthony Koo Committed by Alex Deucher
Browse files

drm/amd/display: set MSA MISC1 bit 6 while sending colorimetry in VSC SDP 



[Why]
It is confusing to sinks if we send VSC SDP only on some format. Today we
signal colorimetry format using MSA while in formats like sRGB.
But when we switch to BT2020 we set the bit to ignore MSA  colorimetry and
instead use the colorimetry information in the VSC SDP.

But if sink supports signaling of colorimetry via VSC SDP we should always
set the MSA MISC1 bit 6, instead of doing so selectively.

[How]
If sink supports signaling of colorimetry via VSC SDP, and we are sending
the colorimetry info via VSC SDP with packet revision 05h, then always
set MSA MISC1 bit 6.

Signed-off-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a5132f97

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+3 −1
Original line number Diff line number Diff line
@@ -4022,7 +4022,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 
			struct dmcu *dmcu = core_dc->res_pool->dmcu;



			stream->psr_version = dmcu->dmcu_version.psr_version;

			mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);

			mod_build_vsc_infopacket(stream,

					&stream->vsc_infopacket,

					&stream->use_vsc_sdp_for_colorimetry);

		}

	}

finish:

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+1 −0
Original line number Diff line number Diff line
@@ -2946,6 +2946,7 @@ void core_link_enable_stream( 
			pipe_ctx->stream_res.stream_enc,

			&stream->timing,

			stream->output_color_space,

			stream->use_vsc_sdp_for_colorimetry,

			stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);



	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/dc_stream.h

+1 −0
Original line number Diff line number Diff line
@@ -164,6 +164,7 @@ struct dc_stream_state { 


	enum view_3d_format view_format;



	bool use_vsc_sdp_for_colorimetry;

	bool ignore_msa_timing_param;

	bool converter_disable_audio;

	uint8_t qs_bit;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

+1 −0
Original line number Diff line number Diff line
@@ -275,6 +275,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( 
	struct stream_encoder *enc,

	struct dc_crtc_timing *crtc_timing,

	enum dc_color_space output_color_space,

	bool use_vsc_sdp_for_colorimetry,

	uint32_t enable_sdp_splitting)

{

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

+2 −4
Original line number Diff line number Diff line
@@ -247,6 +247,7 @@ void enc1_stream_encoder_dp_set_stream_attribute( 
	struct stream_encoder *enc,

	struct dc_crtc_timing *crtc_timing,

	enum dc_color_space output_color_space,

	bool use_vsc_sdp_for_colorimetry,

	uint32_t enable_sdp_splitting)

{

	uint32_t h_active_start;
@@ -312,10 +313,7 @@ void enc1_stream_encoder_dp_set_stream_attribute( 
	 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,

	 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").

	 */

	if ((hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) ||

			(output_color_space == COLOR_SPACE_2020_YCBCR) ||

			(output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) ||

			(output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE))

	if (use_vsc_sdp_for_colorimetry)

		misc1 = misc1 | 0x40;

	else

		misc1 = misc1 & ~0x40;

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