Commit 55dc9723 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'qcom-dts-for-4.20' of... 

Merge tag 'qcom-dts-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt

Qualcomm Device Tree Changes for v4.20

* Fix IRQ constants usage on MSM8974
* Add led, gpio-button, sdcc, and pcie nodes for IPQ8064
* Move/cleanup common nodes for IPQ8064
* Add i2c sensor nodes for MSM8974 Hammerhead
* Fixes for SAW, kpss, opp, pci range, and space/tab on IPQ4019
* Update coresight bindings

* tag 'qcom-dts-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux

:
  ARM: dts: qcom: Update coresight bindings for hardware ports
  ARM: dts: qcom-msm8974: change invalid flag IRQ NONE to valid value
  ARM: dts: qcom: ipq4019: fix space vs tab indenting inside qcom-ipq4019.dtsi
  ARM: dts: qcom: ipq4019: fix PCI range
  ARM: dts: qcom: ipq4019: fix cpu0's qcom,saw2 reg value
  ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq support
  ARM: dts: qcom: ipq4019: use v2 of the kpss bringup mechanism
  ARM: dts: qcom: msm8974-hammerhead: add device tree bindings for ALS / proximity
  ARM: dts: qcom: msm8974-hammerhead: add device tree bindings for mpu6515
  ARM: dts: qcom: Add led and gpio-button nodes to ipq8064 boards
  ARM: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsi
  ARM: dts: qcom: Add sdcc nodes for ipq8064
  ARM: dts: qcom: Add pcie nodes for ipq8064
  ARM: dts: qcom-msm8974: change invalid flag IRQ NONE to valid value
  ARM: dts: qcom-msm8974: use named constant for interrupt flag NONE
  ARM: dts: qcom-msm8974: use named constant for interrupt flag LEVEL HIGH
  ARM: dts: qcom-msm8974: use named constant for interrupt flag EDGE RISING
  ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_SPI
  ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_PPI

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 5908704d ca02f96b

arch/arm/boot/dts/qcom-apq8064.dtsi

+40 −31
Original line number Diff line number Diff line
@@ -1611,13 +1611,14 @@ 
			clocks = <&rpmcc RPM_QDSS_CLK>;

			clock-names = "apb_pclk";



			in-ports {

				port {

					etb_in: endpoint {

					slave-mode;

						remote-endpoint = <&replicator_out0>;

					};

				};

			};

		};



		tpiu@1a03000 {

			compatible = "arm,coresight-tpiu", "arm,primecell";
@@ -1626,13 +1627,14 @@ 
			clocks = <&rpmcc RPM_QDSS_CLK>;

			clock-names = "apb_pclk";



			in-ports {

				port {

					tpiu_in: endpoint {

					slave-mode;

						remote-endpoint = <&replicator_out1>;

					};

				};

			};

		};



		replicator {

			compatible = "arm,coresight-replicator";
@@ -1640,7 +1642,7 @@ 
			clocks = <&rpmcc RPM_QDSS_CLK>;

			clock-names = "apb_pclk";



			ports {

			out-ports {

				#address-cells = <1>;

				#size-cells = <0>;
@@ -1656,10 +1658,11 @@ 
						remote-endpoint = <&tpiu_in>;

					};

				};

				port@2 {

					reg = <0>;

			};



			in-ports {

				port {

					replicator_in: endpoint {

						slave-mode;

						remote-endpoint = <&funnel_out>;

					};

				};
@@ -1673,7 +1676,7 @@ 
			clocks = <&rpmcc RPM_QDSS_CLK>;

			clock-names = "apb_pclk";



			ports {

			in-ports {

				#address-cells = <1>;

				#size-cells = <0>;
@@ -1687,33 +1690,31 @@ 
				port@0 {

					reg = <0>;

					funnel_in0: endpoint {

						slave-mode;

						remote-endpoint = <&etm0_out>;

					};

				};

				port@1 {

					reg = <1>;

					funnel_in1: endpoint {

						slave-mode;

						remote-endpoint = <&etm1_out>;

					};

				};

				port@4 {

					reg = <4>;

					funnel_in4: endpoint {

						slave-mode;

						remote-endpoint = <&etm2_out>;

					};

				};

				port@5 {

					reg = <5>;

					funnel_in5: endpoint {

						slave-mode;

						remote-endpoint = <&etm3_out>;

					};

				};

				port@8 {

					reg = <0>;

			};



			out-ports {

				port {

					funnel_out: endpoint {

						remote-endpoint = <&replicator_in>;

					};
@@ -1730,12 +1731,14 @@ 


			cpu = <&CPU0>;



			out-ports {

				port {

					etm0_out: endpoint {

						remote-endpoint = <&funnel_in0>;

					};

				};

			};

		};



		etm@1a1d000 {

			compatible = "arm,coresight-etm3x", "arm,primecell";
@@ -1746,12 +1749,14 @@ 


			cpu = <&CPU1>;



			out-ports {

				port {

					etm1_out: endpoint {

						remote-endpoint = <&funnel_in1>;

					};

				};

			};

		};



		etm@1a1e000 {

			compatible = "arm,coresight-etm3x", "arm,primecell";
@@ -1762,12 +1767,14 @@ 


			cpu = <&CPU2>;



			out-ports {

				port {

					etm2_out: endpoint {

						remote-endpoint = <&funnel_in4>;

					};

				};

			};

		};



		etm@1a1f000 {

			compatible = "arm,coresight-etm3x", "arm,primecell";
@@ -1778,6 +1785,7 @@ 


			cpu = <&CPU3>;



			out-ports {

				port {

					etm3_out: endpoint {

						remote-endpoint = <&funnel_in5>;
@@ -1786,4 +1794,5 @@ 
			};

		};

	};

};

#include "qcom-apq8064-pins.dtsi"

arch/arm/boot/dts/qcom-ipq4019.dtsi

+75 −68
Original line number Diff line number Diff line
@@ -52,77 +52,84 @@ 
		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			enable-method = "qcom,kpss-acc-v1";

			enable-method = "qcom,kpss-acc-v2";

			next-level-cache = <&L2>;

			qcom,acc = <&acc0>;

			qcom,saw = <&saw0>;

			reg = <0x0>;

			clocks = <&gcc GCC_APPS_CLK_SRC>;

			clock-frequency = <0>;

			operating-points = <

				/* kHz	uV (fixed) */

				48000	1100000

				200000	1100000

				500000	1100000

				716000  1100000

			>;

			clock-latency = <256000>;

			operating-points-v2 = <&cpu0_opp_table>;

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			enable-method = "qcom,kpss-acc-v1";

			enable-method = "qcom,kpss-acc-v2";

			next-level-cache = <&L2>;

			qcom,acc = <&acc1>;

			qcom,saw = <&saw1>;

			reg = <0x1>;

			clocks = <&gcc GCC_APPS_CLK_SRC>;

			clock-frequency = <0>;

			operating-points = <

				/* kHz	uV (fixed) */

				48000	1100000

				200000	1100000

				500000	1100000

				666000	1100000

			>;

			clock-latency = <256000>;

			operating-points-v2 = <&cpu0_opp_table>;

		};



		cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			enable-method = "qcom,kpss-acc-v1";

			enable-method = "qcom,kpss-acc-v2";

			next-level-cache = <&L2>;

			qcom,acc = <&acc2>;

			qcom,saw = <&saw2>;

			reg = <0x2>;

			clocks = <&gcc GCC_APPS_CLK_SRC>;

			clock-frequency = <0>;

			operating-points = <

				/* kHz	uV (fixed) */

				48000	1100000

				200000	1100000

				500000	1100000

				666000	1100000

			>;

			clock-latency = <256000>;

			operating-points-v2 = <&cpu0_opp_table>;

		};



		cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			enable-method = "qcom,kpss-acc-v1";

			enable-method = "qcom,kpss-acc-v2";

			next-level-cache = <&L2>;

			qcom,acc = <&acc3>;

			qcom,saw = <&saw3>;

			reg = <0x3>;

			clocks = <&gcc GCC_APPS_CLK_SRC>;

			clock-frequency = <0>;

			operating-points = <

				/* kHz	uV (fixed) */

				48000	1100000

				200000	1100000

				500000	1100000

				666000	1100000

			>;

			clock-latency = <256000>;

			operating-points-v2 = <&cpu0_opp_table>;

		};



		L2: l2-cache {

			compatible = "cache";

			cache-level = <2>;

		};

	};



	cpu0_opp_table: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp-48000000 {

			opp-hz = /bits/ 64 <48000000>;

			clock-latency-ns = <256000>;

		};

		opp-200000000 {

			opp-hz = /bits/ 64 <200000000>;

			clock-latency-ns = <256000>;

		};

		opp-500000000 {

			opp-hz = /bits/ 64 <500000000>;

			clock-latency-ns = <256000>;

		};

		opp-716000000 {

			opp-hz = /bits/ 64 <716000000>;

			clock-latency-ns = <256000>;

 		};

	};
@@ -292,28 +299,28 @@ 
		};



		acc0: clock-controller@b088000 {

                        compatible = "qcom,kpss-acc-v1";

			compatible = "qcom,kpss-acc-v2";

			reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;

		};



		acc1: clock-controller@b098000 {

                        compatible = "qcom,kpss-acc-v1";

			compatible = "qcom,kpss-acc-v2";

			reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;

		};



		acc2: clock-controller@b0a8000 {

                        compatible = "qcom,kpss-acc-v1";

			compatible = "qcom,kpss-acc-v2";

			reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;

		};



		acc3: clock-controller@b0b8000 {

                        compatible = "qcom,kpss-acc-v1";

			compatible = "qcom,kpss-acc-v2";

			reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;

		};



		saw0: regulator@b089000 {

			compatible = "qcom,saw2";

                        reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;

			reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;

                        regulator;

		};
@@ -387,7 +394,7 @@ 
			#size-cells = <2>;



			ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000

				  0x82000000 0 0x48000000 0x48000000 0 0x10000000>;

				  0x82000000 0 0x40300000 0x40300000 0 0x400000>;



			interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "msi";

arch/arm/boot/dts/qcom-ipq8064-ap148.dts

+7 −76
Original line number Diff line number Diff line
@@ -2,26 +2,8 @@ 
#include "qcom-ipq8064-v1.0.dtsi"



/ {

	model = "Qualcomm IPQ8064/AP148";

	compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";



	aliases {

		serial0 = &gsbi4_serial;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	reserved-memory {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		rsvd@41200000 {

			reg = <0x41200000 0x300000>;

			no-map;

		};

	};

	model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";

	compatible = "qcom,ipq8064-ap148";



	soc {

		pinmux@800000 {
@@ -31,73 +13,22 @@ 
				bias-disable;

			};



			spi_pins: spi_pins {

			buttons_pins: buttons_pins {

				mux {

					pins = "gpio18", "gpio19", "gpio21";

					function = "gsbi5";

					drive-strength = <10>;

					bias-none;

					pins = "gpio54", "gpio65";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		gsbi@16300000 {

			qcom,mode = <GSBI_PROT_I2C_UART>;

			i2c@16380000 {

				status = "ok";

			serial@16340000 {

				status = "ok";

			};



			i2c4: i2c@16380000 {

				status = "ok";



				clock-frequency = <200000>;



				pinctrl-0 = <&i2c4_pins>;

				pinctrl-names = "default";

			};

		};



		gsbi5: gsbi@1a200000 {

			qcom,mode = <GSBI_PROT_SPI>;

			status = "ok";



			spi4: spi@1a280000 {

				status = "ok";

				spi-max-frequency = <50000000>;



				pinctrl-0 = <&spi_pins>;

				pinctrl-names = "default";



				cs-gpios = <&qcom_pinmux 20 0>;



				flash: m25p80@0 {

					compatible = "s25fl256s1";

					#address-cells = <1>;

					#size-cells = <1>;

					spi-max-frequency = <50000000>;

					reg = <0>;



					partition@0 {

						label = "rootfs";

						reg = <0x0 0x1000000>;

					};



					partition@1 {

						label = "scratch";

						reg = <0x1000000 0x1000000>;

					};

				};

			};

		};



		sata-phy@1b400000 {

			status = "ok";

		};



		sata@29000000 {

			ports-implemented = <0x1>;

			status = "ok";

		};

	};

};

arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi

+125 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

#include "qcom-ipq8064.dtsi"

#include <dt-bindings/input/input.h>



/ {

	model = "Qualcomm Technologies, Inc. IPQ8064-v1.0";



	aliases {

		serial0 = &gsbi4_serial;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	soc {

		gsbi@16300000 {

			qcom,mode = <GSBI_PROT_I2C_UART>;

			status = "ok";



			serial@16340000 {

				status = "ok";

			};

		};



		gsbi5: gsbi@1a200000 {

			qcom,mode = <GSBI_PROT_SPI>;

			status = "ok";



			spi4: spi@1a280000 {

				status = "ok";

				spi-max-frequency = <50000000>;



				pinctrl-0 = <&spi_pins>;

				pinctrl-names = "default";



				cs-gpios = <&qcom_pinmux 20 0>;



				flash: m25p80@0 {

					compatible = "s25fl256s1";

					#address-cells = <1>;

					#size-cells = <1>;

					spi-max-frequency = <50000000>;

					reg = <0>;



					partition@0 {

						label = "rootfs";

						reg = <0x0 0x1000000>;

					};



					partition@1 {

						label = "scratch";

						reg = <0x1000000 0x1000000>;

					};

				};

			};

		};



		sata-phy@1b400000 {

			status = "ok";

		};



		sata@29000000 {

			ports-implemented = <0x1>;

			status = "ok";

		};



		gpio_keys {

			compatible = "gpio-keys";

			pinctrl-0 = <&buttons_pins>;

			pinctrl-names = "default";



			button@1 {

				label = "reset";

				linux,code = <KEY_RESTART>;

				gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;

				linux,input-type = <1>;

				debounce-interval = <60>;

			};

			button@2 {

				label = "wps";

				linux,code = <KEY_WPS_BUTTON>;

				gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;

				linux,input-type = <1>;

				debounce-interval = <60>;

			};

		};



		leds {

			compatible = "gpio-leds";

			pinctrl-0 = <&leds_pins>;

			pinctrl-names = "default";



			led@7 {

				label = "led_usb1";

				gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;

				linux,default-trigger = "usbdev";

				default-state = "off";

			};



			led@8 {

				label = "led_usb3";

				gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;

				linux,default-trigger = "usbdev";

				default-state = "off";

			};



			led@9 {

				label = "status_led_fail";

				gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;

				default-state = "off";

			};



			led@26 {

				label = "sata_led";

				gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;

				default-state = "off";

			};



			led@53 {

				label = "status_led_pass";

				gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;

				default-state = "off";

			};

		};

	};

};

arch/arm/boot/dts/qcom-ipq8064.dtsi

+286 −0
Original line number Diff line number Diff line
@@ -2,8 +2,11 @@ 
/dts-v1/;



#include "skeleton.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-ipq806x.h>

#include <dt-bindings/clock/qcom,lcc-ipq806x.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/reset/qcom,gcc-ipq806x.h>

#include <dt-bindings/soc/qcom,gsbi.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -114,6 +117,61 @@ 
			interrupt-controller;

			#interrupt-cells = <2>;

			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;



			pcie0_pins: pcie0_pinmux {

				mux {

					pins = "gpio3";

					function = "pcie1_rst";

					drive-strength = <12>;

					bias-disable;

				};

			};



			pcie1_pins: pcie1_pinmux {

				mux {

					pins = "gpio48";

					function = "pcie2_rst";

					drive-strength = <12>;

					bias-disable;

				};

			};



			pcie2_pins: pcie2_pinmux {

				mux {

					pins = "gpio63";

					function = "pcie3_rst";

					drive-strength = <12>;

					bias-disable;

				};

			};



			spi_pins: spi_pins {

				mux {

					pins = "gpio18", "gpio19", "gpio21";

					function = "gsbi5";

					drive-strength = <10>;

					bias-none;

				};

			};



			leds_pins: leds_pins {

				mux {

					pins = "gpio7", "gpio8", "gpio9",

					       "gpio26", "gpio53";

					function = "gpio";

					drive-strength = <2>;

					bias-pull-down;

					output-low;

				};

			};



			buttons_pins: buttons_pins {

				mux {

					pins = "gpio54";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		intc: interrupt-controller@2000000 {
@@ -373,5 +431,233 @@ 
			#reset-cells = <1>;

		};



		pcie0: pci@1b500000 {

			compatible = "qcom,pcie-ipq8064";

			reg = <0x1b500000 0x1000

			       0x1b502000 0x80

			       0x1b600000 0x100

			       0x0ff00000 0x100000>;

			reg-names = "dbi", "elbi", "parf", "config";

			device_type = "pci";

			linux,pci-domain = <0>;

			bus-range = <0x00 0xff>;

			num-lanes = <1>;

			#address-cells = <3>;

			#size-cells = <2>;



			ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */

				  0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */



			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

					<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

					<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

					<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */



			clocks = <&gcc PCIE_A_CLK>,

				 <&gcc PCIE_H_CLK>,

				 <&gcc PCIE_PHY_CLK>,

				 <&gcc PCIE_AUX_CLK>,

				 <&gcc PCIE_ALT_REF_CLK>;

			clock-names = "core", "iface", "phy", "aux", "ref";



			assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;

			assigned-clock-rates = <100000000>;



			resets = <&gcc PCIE_ACLK_RESET>,

				 <&gcc PCIE_HCLK_RESET>,

				 <&gcc PCIE_POR_RESET>,

				 <&gcc PCIE_PCI_RESET>,

				 <&gcc PCIE_PHY_RESET>,

				 <&gcc PCIE_EXT_RESET>;

			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";



			pinctrl-0 = <&pcie0_pins>;

			pinctrl-names = "default";



			status = "disabled";

			perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;

		};



		pcie1: pci@1b700000 {

			compatible = "qcom,pcie-ipq8064";

			reg = <0x1b700000 0x1000

			       0x1b702000 0x80

			       0x1b800000 0x100

			       0x31f00000 0x100000>;

			reg-names = "dbi", "elbi", "parf", "config";

			device_type = "pci";

			linux,pci-domain = <1>;

			bus-range = <0x00 0xff>;

			num-lanes = <1>;

			#address-cells = <3>;

			#size-cells = <2>;



			ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */

				  0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */



			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

					<0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

					<0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

					<0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */



			clocks = <&gcc PCIE_1_A_CLK>,

				 <&gcc PCIE_1_H_CLK>,

				 <&gcc PCIE_1_PHY_CLK>,

				 <&gcc PCIE_1_AUX_CLK>,

				 <&gcc PCIE_1_ALT_REF_CLK>;

			clock-names = "core", "iface", "phy", "aux", "ref";



			assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;

			assigned-clock-rates = <100000000>;



			resets = <&gcc PCIE_1_ACLK_RESET>,

				 <&gcc PCIE_1_HCLK_RESET>,

				 <&gcc PCIE_1_POR_RESET>,

				 <&gcc PCIE_1_PCI_RESET>,

				 <&gcc PCIE_1_PHY_RESET>,

				 <&gcc PCIE_1_EXT_RESET>;

			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";



			pinctrl-0 = <&pcie1_pins>;

			pinctrl-names = "default";



			status = "disabled";

			perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;

		};



		pcie2: pci@1b900000 {

			compatible = "qcom,pcie-ipq8064";

			reg = <0x1b900000 0x1000

			       0x1b902000 0x80

			       0x1ba00000 0x100

			       0x35f00000 0x100000>;

			reg-names = "dbi", "elbi", "parf", "config";

			device_type = "pci";

			linux,pci-domain = <2>;

			bus-range = <0x00 0xff>;

			num-lanes = <1>;

			#address-cells = <3>;

			#size-cells = <2>;



			ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */

				  0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */



			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

					<0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

					<0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

					<0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */



			clocks = <&gcc PCIE_2_A_CLK>,

				 <&gcc PCIE_2_H_CLK>,

				 <&gcc PCIE_2_PHY_CLK>,

				 <&gcc PCIE_2_AUX_CLK>,

				 <&gcc PCIE_2_ALT_REF_CLK>;

			clock-names = "core", "iface", "phy", "aux", "ref";



			assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;

			assigned-clock-rates = <100000000>;



			resets = <&gcc PCIE_2_ACLK_RESET>,

				 <&gcc PCIE_2_HCLK_RESET>,

				 <&gcc PCIE_2_POR_RESET>,

				 <&gcc PCIE_2_PCI_RESET>,

				 <&gcc PCIE_2_PHY_RESET>,

				 <&gcc PCIE_2_EXT_RESET>;

			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";



			pinctrl-0 = <&pcie2_pins>;

			pinctrl-names = "default";



			status = "disabled";

			perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;

		};



		vsdcc_fixed: vsdcc-regulator {

			compatible = "regulator-fixed";

			regulator-name = "SDCC Power";

			regulator-min-microvolt = <3300000>;

			regulator-max-microvolt = <3300000>;

			regulator-always-on;

		};



		sdcc1bam:dma@12402000 {

			compatible = "qcom,bam-v1.3.0";

			reg = <0x12402000 0x8000>;

			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc SDC1_H_CLK>;

			clock-names = "bam_clk";

			#dma-cells = <1>;

			qcom,ee = <0>;

		};



		sdcc3bam:dma@12182000 {

			compatible = "qcom,bam-v1.3.0";

			reg = <0x12182000 0x8000>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc SDC3_H_CLK>;

			clock-names = "bam_clk";

			#dma-cells = <1>;

			qcom,ee = <0>;

		};



		amba {

			compatible = "simple-bus";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			sdcc@12400000 {

				status          = "disabled";

				compatible      = "arm,pl18x", "arm,primecell";

				arm,primecell-periphid = <0x00051180>;

				reg             = <0x12400000 0x2000>;

				interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "cmd_irq";

				clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;

				clock-names     = "mclk", "apb_pclk";

				bus-width       = <8>;

				max-frequency   = <96000000>;

				non-removable;

				cap-sd-highspeed;

				cap-mmc-highspeed;

				mmc-ddr-1_8v;

				vmmc-supply = <&vsdcc_fixed>;

				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;

				dma-names = "tx", "rx";

			};



			sdcc@12180000 {

				compatible      = "arm,pl18x", "arm,primecell";

				arm,primecell-periphid = <0x00051180>;

				status          = "disabled";

				reg             = <0x12180000 0x2000>;

				interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "cmd_irq";

				clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;

				clock-names     = "mclk", "apb_pclk";

				bus-width       = <8>;

				cap-sd-highspeed;

				cap-mmc-highspeed;

				max-frequency   = <192000000>;

				#mmc-ddr-1_8v;

				sd-uhs-sdr104;

				sd-uhs-ddr50;

				vqmmc-supply = <&vsdcc_fixed>;

				dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;

				dma-names = "tx", "rx";

			};

		};

	};

};

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