Commit 55798360 authored by Michael Turquette's avatar Michael Turquette
Browse files

Merge tag 'v4.12-rockchip-clk1' of... 

Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk driver updates from Heiko Stuebner:

  General rockchip clock changes for 4.12. Contains some new clock-ids
  as well as fixups of the clock-ids on rk3368 timers, which were unused
  and completely wrong (more and differently named timers).
  Also there is one new clock on rk3328 using the muxgrf type, a fix for
  pll enablement which should wait for the pll to lock before continuing,
  some more critical clocks and the rename of the rk1108 to rv1108, as the
  soc seems to have been using a preliminary name before its actual release.
  The plan is to have the driver changes (pinctrl, clk) go through the
  respective maintainer trees and once everything landed in mainline do
  the rename of the devicetree files. With the dts-include change in the
  clock rename, we also keep everything compiling and thus bisectability.

* tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: add pll_wait_lock for pll_enable
  clk: rockchip: rename RK1108 to RV1108
  dt-bindings: rk1108-cru: rename RK1108 to RV1108
  clk: rockchip: mark some rk3368 core-clks as critical
  clk: rockchip: export SCLK_TIMERXX id for timers on rk3368
  clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
  clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs
  clk: rockchip: fix up rk3368 timer-ids
  clk: rockchip: add rk3328 clk_mac2io_ext ID
  clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399
parents 0d4ae360 9be83448

Documentation/devicetree/bindings/clock/rockchip,rk1108-cru.txt→Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt

+6 −6
Original line number Diff line number Diff line 
* Rockchip RK1108 Clock and Reset Unit

* Rockchip RV1108 Clock and Reset Unit



The RK1108 clock controller generates and supplies clock to various

The RV1108 clock controller generates and supplies clock to various

controllers within the SoC and also implements a reset controller for SoC

peripherals.



Required Properties:



- compatible: should be "rockchip,rk1108-cru"

- compatible: should be "rockchip,rv1108-cru"

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.
@@ -19,7 +19,7 @@ Optional Properties: 


Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/rk1108-cru.h headers and can be

preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be

used in device tree sources. Similar macros exist for the reset sources in

these files.
@@ -38,7 +38,7 @@ clock-output-names: 
Example: Clock controller node:



	cru: cru@20200000 {

		compatible = "rockchip,rk1108-cru";

		compatible = "rockchip,rv1108-cru";

		reg = <0x20200000 0x1000>;

		rockchip,grf = <&grf>;
@@ -50,7 +50,7 @@ Example: UART controller node that consumes the clock generated by the clock 
  controller:



	uart0: serial@10230000 {

		compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";

		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";

		reg = <0x10230000 0x100>;

		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

arch/arm/boot/dts/rk1108.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ 
#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/rk1108-cru.h>

#include <dt-bindings/clock/rv1108-cru.h>

#include <dt-bindings/pinctrl/rockchip.h>

/ {

	#address-cells = <1>;

drivers/clk/rockchip/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ obj-y += clk-muxgrf.o 
obj-y	+= clk-ddr.o

obj-$(CONFIG_RESET_CONTROLLER)	+= softrst.o



obj-y	+= clk-rk1108.o

obj-y	+= clk-rv1108.o

obj-y	+= clk-rk3036.o

obj-y	+= clk-rk3188.o

obj-y	+= clk-rk3228.o

drivers/clk/rockchip/clk-pll.c

+3 −0
Original line number Diff line number Diff line
@@ -269,6 +269,7 @@ static int rockchip_rk3036_pll_enable(struct clk_hw *hw) 


	writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),

	       pll->reg_base + RK3036_PLLCON(1));

	rockchip_pll_wait_lock(pll);



	return 0;

}
@@ -501,6 +502,7 @@ static int rockchip_rk3066_pll_enable(struct clk_hw *hw) 


	writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),

	       pll->reg_base + RK3066_PLLCON(3));

	rockchip_pll_wait_lock(pll);



	return 0;

}
@@ -746,6 +748,7 @@ static int rockchip_rk3399_pll_enable(struct clk_hw *hw) 


	writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),

	       pll->reg_base + RK3399_PLLCON(3));

	rockchip_rk3399_pll_wait_lock(pll);



	return 0;

}

drivers/clk/rockchip/clk-rk3328.c

+9 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#include <dt-bindings/clock/rk3328-cru.h>

#include "clk.h"



#define RK3328_GRF_SOC_CON4		0x410

#define RK3328_GRF_SOC_STATUS0		0x480

#define RK3328_GRF_MAC_CON1		0x904

#define RK3328_GRF_MAC_CON2		0x908
@@ -214,6 +215,8 @@ PNAME(mux_mac2io_src_p) = { "clk_mac2io_src", 
				    "gmac_clkin" };

PNAME(mux_mac2phy_src_p)	= { "clk_mac2phy_src",

				    "phy_50m_out" };

PNAME(mux_mac2io_ext_p)		= { "clk_mac2io",

				    "gmac_clkin" };



static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = {

	[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
@@ -680,6 +683,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
	COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0,

			RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,

			RK3328_CLKGATE_CON(3), 5, GFLAGS),

	MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT,

			RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),

	MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT,

			RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),



	COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,

			RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
@@ -691,6 +698,8 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
	COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0,

			RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,

			RK3328_CLKGATE_CON(9), 2, GFLAGS),

	MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT,

			RK3328_GRF_MAC_CON2, 10, 1, MFLAGS),



	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),

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