Commit 0d4ae360 authored by Michael Turquette's avatar Michael Turquette
Browse files

Merge tag 'clk-renesas-for-v4.12-tag2' of... 

Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add support for the Clock Pulse Generator / Module Standby and
    Software Reset module on revision ES2.0 of the R-Car H3 SoC, which
    differs from ES1.x in some areas.
  - Add IMR clocks for R-Car H3 and M3-W,
  - Add workaround for PLL0/2/4 errata on R-Car H3 ES1.0,
  - Small fixes and cleanups.

* tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0
  clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
  clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions
  clk: renesas: cpg-mssr: Add support for fixing up clock tables
  clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0
  clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
  clk: renesas: r8a7796: Reformat core clock table
  clk: renesas: r8a7795: Reformat core clock table
  clk: renesas: r8a7796: Correct name of watchdog clock
  clk: renesas: r8a7795: Correct name of watchdog clock
  clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs
  clk: renesas: r8a7796: Add IMR clocks
  clk: renesas: r8a7795: Add IMR clocks
parents f37753e2 bb195306

drivers/clk/renesas/r8a7795-cpg-mssr.c

+163 −58
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/soc/renesas/rcar-rst.h>

#include <linux/sys_soc.h>



#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
@@ -24,7 +25,7 @@ 


enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R8A7795_CLK_OSC,

	LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,



	/* External Input Clocks */

	CLK_EXTAL,
@@ -51,7 +52,7 @@ enum clk_ids { 
	MOD_CLK_BASE

};



static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {

static struct cpg_core_clk r8a7795_core_clks[] __initdata = {

	/* External Clock Inputs */

	DEF_INPUT("extal",      CLK_EXTAL),

	DEF_INPUT("extalr",     CLK_EXTALR),
@@ -78,7 +79,12 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { 
	DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),

	DEF_FIXED("zx",         R8A7795_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),

	DEF_FIXED("s0d1",       R8A7795_CLK_S0D1,  CLK_S0,         1, 1),

	DEF_FIXED("s0d2",       R8A7795_CLK_S0D2,  CLK_S0,         2, 1),

	DEF_FIXED("s0d3",       R8A7795_CLK_S0D3,  CLK_S0,         3, 1),

	DEF_FIXED("s0d4",       R8A7795_CLK_S0D4,  CLK_S0,         4, 1),

	DEF_FIXED("s0d6",       R8A7795_CLK_S0D6,  CLK_S0,         6, 1),

	DEF_FIXED("s0d8",       R8A7795_CLK_S0D8,  CLK_S0,         8, 1),

	DEF_FIXED("s0d12",      R8A7795_CLK_S0D12, CLK_S0,        12, 1),

	DEF_FIXED("s1d1",       R8A7795_CLK_S1D1,  CLK_S1,         1, 1),

	DEF_FIXED("s1d2",       R8A7795_CLK_S1D2,  CLK_S1,         2, 1),

	DEF_FIXED("s1d4",       R8A7795_CLK_S1D4,  CLK_S1,         4, 1),
@@ -89,18 +95,18 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { 
	DEF_FIXED("s3d2",       R8A7795_CLK_S3D2,  CLK_S3,         2, 1),

	DEF_FIXED("s3d4",       R8A7795_CLK_S3D4,  CLK_S3,         4, 1),



	DEF_GEN3_SD("sd0",      R8A7795_CLK_SD0,   CLK_SDSRC,     0x0074),

	DEF_GEN3_SD("sd1",      R8A7795_CLK_SD1,   CLK_SDSRC,     0x0078),

	DEF_GEN3_SD("sd2",      R8A7795_CLK_SD2,   CLK_SDSRC,     0x0268),

	DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   CLK_SDSRC,     0x026c),

	DEF_GEN3_SD("sd0",      R8A7795_CLK_SD0,   CLK_SDSRC,     0x074),

	DEF_GEN3_SD("sd1",      R8A7795_CLK_SD1,   CLK_SDSRC,     0x078),

	DEF_GEN3_SD("sd2",      R8A7795_CLK_SD2,   CLK_SDSRC,     0x268),

	DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   CLK_SDSRC,     0x26c),



	DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),



	DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),

	DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),

	DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),

	DEF_DIV6P1("csi0",      R8A7795_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),

	DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),

	DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),



	DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),

	DEF_DIV6_RO("r_int",    CLK_RINT,          CLK_EXTAL, CPG_RCKCR, 32),
@@ -108,10 +114,10 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { 
	DEF_BASE("r",           R8A7795_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),

};



static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {

	DEF_MOD("fdp1-2",		 117,	R8A7795_CLK_S2D1),

	DEF_MOD("fdp1-1",		 118,	R8A7795_CLK_S2D1),

	DEF_MOD("fdp1-0",		 119,	R8A7795_CLK_S2D1),

static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {

	DEF_MOD("fdp1-2",		 117,	R8A7795_CLK_S2D1), /* ES1.x */

	DEF_MOD("fdp1-1",		 118,	R8A7795_CLK_S0D1),

	DEF_MOD("fdp1-0",		 119,	R8A7795_CLK_S0D1),

	DEF_MOD("scif5",		 202,	R8A7795_CLK_S3D4),

	DEF_MOD("scif4",		 203,	R8A7795_CLK_S3D4),

	DEF_MOD("scif3",		 204,	R8A7795_CLK_S3D4),
@@ -121,9 +127,9 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { 
	DEF_MOD("msiof2",		 209,	R8A7795_CLK_MSO),

	DEF_MOD("msiof1",		 210,	R8A7795_CLK_MSO),

	DEF_MOD("msiof0",		 211,	R8A7795_CLK_MSO),

	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S3D1),

	DEF_MOD("sys-dmac1",		 218,	R8A7795_CLK_S3D1),

	DEF_MOD("sys-dmac0",		 219,	R8A7795_CLK_S3D1),

	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S0D3),

	DEF_MOD("sys-dmac1",		 218,	R8A7795_CLK_S0D3),

	DEF_MOD("sys-dmac0",		 219,	R8A7795_CLK_S0D3),

	DEF_MOD("cmt3",			 300,	R8A7795_CLK_R),

	DEF_MOD("cmt2",			 301,	R8A7795_CLK_R),

	DEF_MOD("cmt1",			 302,	R8A7795_CLK_R),
@@ -135,15 +141,15 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { 
	DEF_MOD("sdif0",		 314,	R8A7795_CLK_SD0),

	DEF_MOD("pcie1",		 318,	R8A7795_CLK_S3D1),

	DEF_MOD("pcie0",		 319,	R8A7795_CLK_S3D1),

	DEF_MOD("usb3-if1",		 327,	R8A7795_CLK_S3D1),

	DEF_MOD("usb3-if1",		 327,	R8A7795_CLK_S3D1), /* ES1.x */

	DEF_MOD("usb3-if0",		 328,	R8A7795_CLK_S3D1),

	DEF_MOD("usb-dmac0",		 330,	R8A7795_CLK_S3D1),

	DEF_MOD("usb-dmac1",		 331,	R8A7795_CLK_S3D1),

	DEF_MOD("rwdt0",		 402,	R8A7795_CLK_R),

	DEF_MOD("rwdt",			 402,	R8A7795_CLK_R),

	DEF_MOD("intc-ex",		 407,	R8A7795_CLK_CP),

	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S3D1),

	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S3D4),

	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S3D4),

	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S0D3),

	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S0D3),

	DEF_MOD("drif7",		 508,	R8A7795_CLK_S3D2),

	DEF_MOD("drif6",		 509,	R8A7795_CLK_S3D2),

	DEF_MOD("drif5",		 510,	R8A7795_CLK_S3D2),
@@ -159,35 +165,35 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { 
	DEF_MOD("hscif0",		 520,	R8A7795_CLK_S3D1),

	DEF_MOD("thermal",		 522,	R8A7795_CLK_CP),

	DEF_MOD("pwm",			 523,	R8A7795_CLK_S3D4),

	DEF_MOD("fcpvd3",		 600,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvd2",		 601,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvd1",		 602,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvd0",		 603,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvb1",		 606,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvb0",		 607,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvi2",		 609,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvi1",		 610,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvi0",		 611,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpf2",		 613,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpf1",		 614,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpf0",		 615,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpci1",		 616,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpci0",		 617,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpcs",		 619,	R8A7795_CLK_S2D1),

	DEF_MOD("vspd3",		 620,	R8A7795_CLK_S2D1),

	DEF_MOD("vspd2",		 621,	R8A7795_CLK_S2D1),

	DEF_MOD("vspd1",		 622,	R8A7795_CLK_S2D1),

	DEF_MOD("vspd0",		 623,	R8A7795_CLK_S2D1),

	DEF_MOD("vspbc",		 624,	R8A7795_CLK_S2D1),

	DEF_MOD("vspbd",		 626,	R8A7795_CLK_S2D1),

	DEF_MOD("vspi2",		 629,	R8A7795_CLK_S2D1),

	DEF_MOD("vspi1",		 630,	R8A7795_CLK_S2D1),

	DEF_MOD("vspi0",		 631,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvd3",		 600,	R8A7795_CLK_S2D1), /* ES1.x */

	DEF_MOD("fcpvd2",		 601,	R8A7795_CLK_S0D2),

	DEF_MOD("fcpvd1",		 602,	R8A7795_CLK_S0D2),

	DEF_MOD("fcpvd0",		 603,	R8A7795_CLK_S0D2),

	DEF_MOD("fcpvb1",		 606,	R8A7795_CLK_S0D1),

	DEF_MOD("fcpvb0",		 607,	R8A7795_CLK_S0D1),

	DEF_MOD("fcpvi2",		 609,	R8A7795_CLK_S2D1), /* ES1.x */

	DEF_MOD("fcpvi1",		 610,	R8A7795_CLK_S0D1),

	DEF_MOD("fcpvi0",		 611,	R8A7795_CLK_S0D1),

	DEF_MOD("fcpf2",		 613,	R8A7795_CLK_S2D1), /* ES1.x */

	DEF_MOD("fcpf1",		 614,	R8A7795_CLK_S0D1),

	DEF_MOD("fcpf0",		 615,	R8A7795_CLK_S0D1),

	DEF_MOD("fcpci1",		 616,	R8A7795_CLK_S2D1), /* ES1.x */

	DEF_MOD("fcpci0",		 617,	R8A7795_CLK_S2D1), /* ES1.x */

	DEF_MOD("fcpcs",		 619,	R8A7795_CLK_S0D1),

	DEF_MOD("vspd3",		 620,	R8A7795_CLK_S2D1), /* ES1.x */

	DEF_MOD("vspd2",		 621,	R8A7795_CLK_S0D2),

	DEF_MOD("vspd1",		 622,	R8A7795_CLK_S0D2),

	DEF_MOD("vspd0",		 623,	R8A7795_CLK_S0D2),

	DEF_MOD("vspbc",		 624,	R8A7795_CLK_S0D1),

	DEF_MOD("vspbd",		 626,	R8A7795_CLK_S0D1),

	DEF_MOD("vspi2",		 629,	R8A7795_CLK_S2D1), /* ES1.x */

	DEF_MOD("vspi1",		 630,	R8A7795_CLK_S0D1),

	DEF_MOD("vspi0",		 631,	R8A7795_CLK_S0D1),

	DEF_MOD("ehci2",		 701,	R8A7795_CLK_S3D4),

	DEF_MOD("ehci1",		 702,	R8A7795_CLK_S3D4),

	DEF_MOD("ehci0",		 703,	R8A7795_CLK_S3D4),

	DEF_MOD("hsusb",		 704,	R8A7795_CLK_S3D4),

	DEF_MOD("csi21",		 713,	R8A7795_CLK_CSI0),

	DEF_MOD("csi21",		 713,	R8A7795_CLK_CSI0), /* ES1.x */

	DEF_MOD("csi20",		 714,	R8A7795_CLK_CSI0),

	DEF_MOD("csi41",		 715,	R8A7795_CLK_CSI0),

	DEF_MOD("csi40",		 716,	R8A7795_CLK_CSI0),
@@ -198,16 +204,20 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { 
	DEF_MOD("lvds",			 727,	R8A7795_CLK_S0D4),

	DEF_MOD("hdmi1",		 728,	R8A7795_CLK_HDMI),

	DEF_MOD("hdmi0",		 729,	R8A7795_CLK_HDMI),

	DEF_MOD("vin7",			 804,	R8A7795_CLK_S2D1),

	DEF_MOD("vin6",			 805,	R8A7795_CLK_S2D1),

	DEF_MOD("vin5",			 806,	R8A7795_CLK_S2D1),

	DEF_MOD("vin4",			 807,	R8A7795_CLK_S2D1),

	DEF_MOD("vin3",			 808,	R8A7795_CLK_S2D1),

	DEF_MOD("vin2",			 809,	R8A7795_CLK_S2D1),

	DEF_MOD("vin1",			 810,	R8A7795_CLK_S2D1),

	DEF_MOD("vin0",			 811,	R8A7795_CLK_S2D1),

	DEF_MOD("etheravb",		 812,	R8A7795_CLK_S3D2),

	DEF_MOD("vin7",			 804,	R8A7795_CLK_S0D2),

	DEF_MOD("vin6",			 805,	R8A7795_CLK_S0D2),

	DEF_MOD("vin5",			 806,	R8A7795_CLK_S0D2),

	DEF_MOD("vin4",			 807,	R8A7795_CLK_S0D2),

	DEF_MOD("vin3",			 808,	R8A7795_CLK_S0D2),

	DEF_MOD("vin2",			 809,	R8A7795_CLK_S0D2),

	DEF_MOD("vin1",			 810,	R8A7795_CLK_S0D2),

	DEF_MOD("vin0",			 811,	R8A7795_CLK_S0D2),

	DEF_MOD("etheravb",		 812,	R8A7795_CLK_S0D6),

	DEF_MOD("sata0",		 815,	R8A7795_CLK_S3D2),

	DEF_MOD("imr3",			 820,	R8A7795_CLK_S0D2),

	DEF_MOD("imr2",			 821,	R8A7795_CLK_S0D2),

	DEF_MOD("imr1",			 822,	R8A7795_CLK_S0D2),

	DEF_MOD("imr0",			 823,	R8A7795_CLK_S0D2),

	DEF_MOD("gpio7",		 905,	R8A7795_CLK_CP),

	DEF_MOD("gpio6",		 906,	R8A7795_CLK_CP),

	DEF_MOD("gpio5",		 907,	R8A7795_CLK_CP),
@@ -310,6 +320,82 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { 
	{ 2,		192,		192,	},

};



static const struct soc_device_attribute r8a7795es1[] __initconst = {

	{ .soc_id = "r8a7795", .revision = "ES1.*" },

	{ /* sentinel */ }

};





	/*

	 * Fixups for R-Car H3 ES1.x

	 */



static const unsigned int r8a7795es1_mod_nullify[] __initconst = {

	MOD_CLK_ID(326),			/* USB-DMAC3-0 */

	MOD_CLK_ID(329),			/* USB-DMAC3-1 */

	MOD_CLK_ID(700),			/* EHCI/OHCI3 */

	MOD_CLK_ID(705),			/* HS-USB-IF3 */



};



static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {

	{ MOD_CLK_ID(118), R8A7795_CLK_S2D1 },	/* FDP1-1 */

	{ MOD_CLK_ID(119), R8A7795_CLK_S2D1 },	/* FDP1-0 */

	{ MOD_CLK_ID(217), R8A7795_CLK_S3D1 },	/* SYS-DMAC2 */

	{ MOD_CLK_ID(218), R8A7795_CLK_S3D1 },	/* SYS-DMAC1 */

	{ MOD_CLK_ID(219), R8A7795_CLK_S3D1 },	/* SYS-DMAC0 */

	{ MOD_CLK_ID(501), R8A7795_CLK_S3D1 },	/* AUDMAC1 */

	{ MOD_CLK_ID(502), R8A7795_CLK_S3D1 },	/* AUDMAC0 */

	{ MOD_CLK_ID(601), R8A7795_CLK_S2D1 },	/* FCPVD2 */

	{ MOD_CLK_ID(602), R8A7795_CLK_S2D1 },	/* FCPVD1 */

	{ MOD_CLK_ID(603), R8A7795_CLK_S2D1 },	/* FCPVD0 */

	{ MOD_CLK_ID(606), R8A7795_CLK_S2D1 },	/* FCPVB1 */

	{ MOD_CLK_ID(607), R8A7795_CLK_S2D1 },	/* FCPVB0 */

	{ MOD_CLK_ID(610), R8A7795_CLK_S2D1 },	/* FCPVI1 */

	{ MOD_CLK_ID(611), R8A7795_CLK_S2D1 },	/* FCPVI0 */

	{ MOD_CLK_ID(614), R8A7795_CLK_S2D1 },	/* FCPF1 */

	{ MOD_CLK_ID(615), R8A7795_CLK_S2D1 },	/* FCPF0 */

	{ MOD_CLK_ID(619), R8A7795_CLK_S2D1 },	/* FCPCS */

	{ MOD_CLK_ID(621), R8A7795_CLK_S2D1 },	/* VSPD2 */

	{ MOD_CLK_ID(622), R8A7795_CLK_S2D1 },	/* VSPD1 */

	{ MOD_CLK_ID(623), R8A7795_CLK_S2D1 },	/* VSPD0 */

	{ MOD_CLK_ID(624), R8A7795_CLK_S2D1 },	/* VSPBC */

	{ MOD_CLK_ID(626), R8A7795_CLK_S2D1 },	/* VSPBD */

	{ MOD_CLK_ID(630), R8A7795_CLK_S2D1 },	/* VSPI1 */

	{ MOD_CLK_ID(631), R8A7795_CLK_S2D1 },	/* VSPI0 */

	{ MOD_CLK_ID(804), R8A7795_CLK_S2D1 },	/* VIN7 */

	{ MOD_CLK_ID(805), R8A7795_CLK_S2D1 },	/* VIN6 */

	{ MOD_CLK_ID(806), R8A7795_CLK_S2D1 },	/* VIN5 */

	{ MOD_CLK_ID(807), R8A7795_CLK_S2D1 },	/* VIN4 */

	{ MOD_CLK_ID(808), R8A7795_CLK_S2D1 },	/* VIN3 */

	{ MOD_CLK_ID(809), R8A7795_CLK_S2D1 },	/* VIN2 */

	{ MOD_CLK_ID(810), R8A7795_CLK_S2D1 },	/* VIN1 */

	{ MOD_CLK_ID(811), R8A7795_CLK_S2D1 },	/* VIN0 */

	{ MOD_CLK_ID(812), R8A7795_CLK_S3D2 },	/* EAVB-IF */

	{ MOD_CLK_ID(820), R8A7795_CLK_S2D1 },	/* IMR3 */

	{ MOD_CLK_ID(821), R8A7795_CLK_S2D1 },	/* IMR2 */

	{ MOD_CLK_ID(822), R8A7795_CLK_S2D1 },	/* IMR1 */

	{ MOD_CLK_ID(823), R8A7795_CLK_S2D1 },	/* IMR0 */

};





	/*

	 * Fixups for R-Car H3 ES2.x

	 */



static const unsigned int r8a7795es2_mod_nullify[] __initconst = {

	MOD_CLK_ID(117),			/* FDP1-2 */

	MOD_CLK_ID(327),			/* USB3-IF1 */

	MOD_CLK_ID(600),			/* FCPVD3 */

	MOD_CLK_ID(609),			/* FCPVI2 */

	MOD_CLK_ID(613),			/* FCPF2 */

	MOD_CLK_ID(616),			/* FCPCI1 */

	MOD_CLK_ID(617),			/* FCPCI0 */

	MOD_CLK_ID(620),			/* VSPD3 */

	MOD_CLK_ID(629),			/* VSPI2 */

	MOD_CLK_ID(713),			/* CSI21 */

};



static int __init r8a7795_cpg_mssr_init(struct device *dev)

{

	const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
@@ -326,7 +412,26 @@ static int __init r8a7795_cpg_mssr_init(struct device *dev) 
		return -EINVAL;

	}



	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR);

	if (soc_device_match(r8a7795es1)) {

		cpg_core_nullify_range(r8a7795_core_clks,

				       ARRAY_SIZE(r8a7795_core_clks),

				       R8A7795_CLK_S0D2, R8A7795_CLK_S0D12);

		mssr_mod_nullify(r8a7795_mod_clks,

				 ARRAY_SIZE(r8a7795_mod_clks),

				 r8a7795es1_mod_nullify,

				 ARRAY_SIZE(r8a7795es1_mod_nullify));

		mssr_mod_reparent(r8a7795_mod_clks,

				  ARRAY_SIZE(r8a7795_mod_clks),

				  r8a7795es1_mod_reparent,

				  ARRAY_SIZE(r8a7795es1_mod_reparent));

	} else {

		mssr_mod_nullify(r8a7795_mod_clks,

				 ARRAY_SIZE(r8a7795_mod_clks),

				 r8a7795es2_mod_nullify,

				 ARRAY_SIZE(r8a7795es2_mod_nullify));

	}



	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);

}



const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {

drivers/clk/renesas/r8a7796-cpg-mssr.c

+10 −8
Original line number Diff line number Diff line
@@ -95,10 +95,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 
	DEF_FIXED("s3d2",       R8A7796_CLK_S3D2,  CLK_S3,         2, 1),

	DEF_FIXED("s3d4",       R8A7796_CLK_S3D4,  CLK_S3,         4, 1),



	DEF_GEN3_SD("sd0",      R8A7796_CLK_SD0,   CLK_SDSRC,    0x0074),

	DEF_GEN3_SD("sd1",      R8A7796_CLK_SD1,   CLK_SDSRC,    0x0078),

	DEF_GEN3_SD("sd2",      R8A7796_CLK_SD2,   CLK_SDSRC,    0x0268),

	DEF_GEN3_SD("sd3",      R8A7796_CLK_SD3,   CLK_SDSRC,    0x026c),

	DEF_GEN3_SD("sd0",      R8A7796_CLK_SD0,   CLK_SDSRC,     0x074),

	DEF_GEN3_SD("sd1",      R8A7796_CLK_SD1,   CLK_SDSRC,     0x078),

	DEF_GEN3_SD("sd2",      R8A7796_CLK_SD2,   CLK_SDSRC,     0x268),

	DEF_GEN3_SD("sd3",      R8A7796_CLK_SD3,   CLK_SDSRC,     0x26c),



	DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),
@@ -135,7 +135,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("sdif2",		 312,	R8A7796_CLK_SD2),

	DEF_MOD("sdif1",		 313,	R8A7796_CLK_SD1),

	DEF_MOD("sdif0",		 314,	R8A7796_CLK_SD0),

	DEF_MOD("rwdt0",		 402,	R8A7796_CLK_R),

	DEF_MOD("rwdt",			 402,	R8A7796_CLK_R),

	DEF_MOD("intc-ap",		 408,	R8A7796_CLK_S3D1),

	DEF_MOD("drif7",		 508,	R8A7796_CLK_S3D2),

	DEF_MOD("drif6",		 509,	R8A7796_CLK_S3D2),
@@ -179,6 +179,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("vin1",			 810,	R8A7796_CLK_S0D2),

	DEF_MOD("vin0",			 811,	R8A7796_CLK_S0D2),

	DEF_MOD("etheravb",		 812,	R8A7796_CLK_S0D6),

	DEF_MOD("imr1",			 822,	R8A7796_CLK_S0D2),

	DEF_MOD("imr0",			 823,	R8A7796_CLK_S0D2),

	DEF_MOD("gpio7",		 905,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio6",		 906,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio5",		 907,	R8A7796_CLK_S3D4),
@@ -271,7 +273,7 @@ static int __init r8a7796_cpg_mssr_init(struct device *dev) 
		return -EINVAL;

	}



	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR);

	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);

}



const struct cpg_mssr_info r8a7796_cpg_mssr_info __initconst = {

drivers/clk/renesas/rcar-gen3-cpg.c

+53 −11
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#include <linux/init.h>

#include <linux/io.h>

#include <linux/slab.h>

#include <linux/sys_soc.h>



#include "renesas-cpg-mssr.h"

#include "rcar-gen3-cpg.h"
@@ -247,6 +248,27 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, 


static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;

static unsigned int cpg_clk_extalr __initdata;

static u32 cpg_mode __initdata;

static u32 cpg_quirks __initdata;



#define PLL_ERRATA	BIT(0)		/* Missing PLL0/2/4 post-divider */

#define RCKCR_CKSEL	BIT(1)		/* Manual RCLK parent selection */



static const struct soc_device_attribute cpg_quirks_match[] __initconst = {

	{

		.soc_id = "r8a7795", .revision = "ES1.0",

		.data = (void *)(PLL_ERRATA | RCKCR_CKSEL),

	},

	{

		.soc_id = "r8a7795", .revision = "ES1.*",

		.data = (void *)RCKCR_CKSEL,

	},

	{

		.soc_id = "r8a7796", .revision = "ES1.0",

		.data = (void *)RCKCR_CKSEL,

	},

	{ /* sentinel */ }

};



struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,

	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
@@ -275,6 +297,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 
		 */

		value = readl(base + CPG_PLL0CR);

		mult = (((value >> 24) & 0x7f) + 1) * 2;

		if (cpg_quirks & PLL_ERRATA)

			mult *= 2;

		break;



	case CLK_TYPE_GEN3_PLL1:
@@ -290,6 +314,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 
		 */

		value = readl(base + CPG_PLL2CR);

		mult = (((value >> 24) & 0x7f) + 1) * 2;

		if (cpg_quirks & PLL_ERRATA)

			mult *= 2;

		break;



	case CLK_TYPE_GEN3_PLL3:
@@ -305,12 +331,15 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 
		 */

		value = readl(base + CPG_PLL4CR);

		mult = (((value >> 24) & 0x7f) + 1) * 2;

		if (cpg_quirks & PLL_ERRATA)

			mult *= 2;

		break;



	case CLK_TYPE_GEN3_SD:

		return cpg_sd_clk_register(core, base, __clk_get_name(parent));



	case CLK_TYPE_GEN3_R:

		if (cpg_quirks & RCKCR_CKSEL) {

			/*

			 * RINT is default.

			 * Only if EXTALR is populated, we switch to it.
@@ -324,6 +353,12 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 


			writel(value, base + CPG_RCKCR);

			break;

		}



		/* Select parent clock of RCLK by MD28 */

		if (cpg_mode & BIT(28))

			parent = clks[cpg_clk_extalr];

		break;



	default:

		return ERR_PTR(-EINVAL);
@@ -334,9 +369,16 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 
}



int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,

			      unsigned int clk_extalr)

			      unsigned int clk_extalr, u32 mode)

{

	const struct soc_device_attribute *attr;



	cpg_pll_config = config;

	cpg_clk_extalr = clk_extalr;

	cpg_mode = mode;

	attr = soc_device_match(cpg_quirks_match);

	if (attr)

		cpg_quirks = (uintptr_t)attr->data;

	pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);

	return 0;

}

drivers/clk/renesas/rcar-gen3-cpg.h

+1 −1
Original line number Diff line number Diff line
@@ -37,6 +37,6 @@ struct clk *rcar_gen3_cpg_clk_register(struct device *dev, 
	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,

	struct clk **clks, void __iomem *base);

int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,

		       unsigned int clk_extalr);

		       unsigned int clk_extalr, u32 mode);



#endif

drivers/clk/renesas/renesas-cpg-mssr.c

+50 −0
Original line number Diff line number Diff line
@@ -265,6 +265,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, 
	WARN_DEBUG(id >= priv->num_core_clks);

	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);



	if (!core->name) {

		/* Skip NULLified clock */

		return;

	}



	switch (core->type) {

	case CLK_TYPE_IN:

		clk = of_clk_get_by_name(priv->dev->of_node, core->name);
@@ -335,6 +340,11 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, 
	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);

	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);



	if (!mod->name) {

		/* Skip NULLified clock */

		return;

	}



	parent = priv->clks[mod->parent];

	if (IS_ERR(parent)) {

		clk = parent;
@@ -734,5 +744,45 @@ static int __init cpg_mssr_init(void) 


subsys_initcall(cpg_mssr_init);



void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,

				   unsigned int num_core_clks,

				   unsigned int first_clk,

				   unsigned int last_clk)

{

	unsigned int i;



	for (i = 0; i < num_core_clks; i++)

		if (core_clks[i].id >= first_clk &&

		    core_clks[i].id <= last_clk)

			core_clks[i].name = NULL;

}



void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,

			     unsigned int num_mod_clks,

			     const unsigned int *clks, unsigned int n)

{

	unsigned int i, j;



	for (i = 0, j = 0; i < num_mod_clks && j < n; i++)

		if (mod_clks[i].id == clks[j]) {

			mod_clks[i].name = NULL;

			j++;

		}

}



void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,

			      unsigned int num_mod_clks,

			      const struct mssr_mod_reparent *clks,

			      unsigned int n)

{

	unsigned int i, j;



	for (i = 0, j = 0; i < num_mod_clks && j < n; i++)

		if (mod_clks[i].id == clks[j].clk) {

			mod_clks[i].parent = clks[j].parent;

			j++;

		}

}



MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");

MODULE_LICENSE("GPL v2");

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