Commit 55692ced authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v5.3-rockchip-clk1' of... 

Merge tag 'v5.3-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - New clock-ids+exports for two clocks
 - Cleanup for some boilerplate code for clocks we cannot really control
   from the kernel, but want to define separately to match the
   hardware-description (watchdog in secure-grf)
 - Improvement in mmc phase calculation and cleanup of some rate defintions

* tag 'v5.3-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: export HDMIPHY clock on rk3228
  clk: rockchip: add watchdog pclk on rk3328
  clk: rockchip: add clock id for hdmi_phy special clock on rk3228
  clk: rockchip: add clock id for watchdog pclk on rk3328
  clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro
  clk: rockchip: add a type from SGRF-controlled gate clocks
  clk: rockchip: Remove 48 MHz PLL rate from rk3288
  clk: rockchip: add 1.464GHz cpu-clock rate to rk3228
  clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase()
  clk: rockchip: Don't yell about bad mmc phases when getting
  clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation
parents a188339c 794e94ca

drivers/clk/rockchip/clk-mmc-phase.c

+6 −8
Original line number Original line Diff line number Diff line
@@ -55,29 +55,27 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw, 
static int rockchip_mmc_get_phase(struct clk_hw *hw)

static int rockchip_mmc_get_phase(struct clk_hw *hw)

{

{

	struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);

	struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);

	unsigned long rate = clk_get_rate(hw->clk);

	unsigned long rate = clk_hw_get_rate(hw);

	u32 raw_value;

	u32 raw_value;

	u16 degrees;

	u16 degrees;

	u32 delay_num = 0;

	u32 delay_num = 0;





	/* See the comment for rockchip_mmc_set_phase below */

	/* See the comment for rockchip_mmc_set_phase below */

	if (!rate) {

	if (!rate)

		pr_err("%s: invalid clk rate\n", __func__);

		return -EINVAL;

		return -EINVAL;

	}





	raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);

	raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);





	degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;

	degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;





	if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {

	if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {

		/* degrees/delaynum * 10000 */

		/* degrees/delaynum * 1000000 */

		unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *

		unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *

					36 * (rate / 1000000);

					36 * (rate / 10000);





		delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);

		delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);

		delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;

		delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;

		degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);

		degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000);

	}

	}





	return degrees % 360;

	return degrees % 360;
@@ -86,7 +84,7 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw) 
static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)

static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)

{

{

	struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);

	struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);

	unsigned long rate = clk_get_rate(hw->clk);

	unsigned long rate = clk_hw_get_rate(hw);

	u8 nineties, remainder;

	u8 nineties, remainder;

	u8 delay_num;

	u8 delay_num;

	u32 raw_value;

	u32 raw_value;

drivers/clk/rockchip/clk-px30.c

+3 −9
Original line number Original line Diff line number Diff line
@@ -803,6 +803,9 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = { 
	GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS),

	GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS),

	GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS),

	GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS),





	/* aclk_dmac is controlled by sgrf_soc_con1[11]. */

	SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"),



	GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS),

	GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS),

	GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS),

	GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS),

	GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS),

	GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS),
@@ -966,7 +969,6 @@ static void __init px30_clk_init(struct device_node *np) 
{

{

	struct rockchip_clk_provider *ctx;

	struct rockchip_clk_provider *ctx;

	void __iomem *reg_base;

	void __iomem *reg_base;

	struct clk *clk;





	reg_base = of_iomap(np, 0);

	reg_base = of_iomap(np, 0);

	if (!reg_base) {

	if (!reg_base) {
@@ -981,14 +983,6 @@ static void __init px30_clk_init(struct device_node *np) 
		return;

		return;

	}

	}





	/* aclk_dmac is controlled by sgrf_soc_con1[11]. */

	clk = clk_register_fixed_factor(NULL, "aclk_dmac", "aclk_bus_pre", 0, 1, 1);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock aclk_dmac: %ld\n",

			__func__, PTR_ERR(clk));

	else

		rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC);



	rockchip_clk_register_plls(ctx, px30_pll_clks,

	rockchip_clk_register_plls(ctx, px30_pll_clks,

				   ARRAY_SIZE(px30_pll_clks),

				   ARRAY_SIZE(px30_pll_clks),

				   PX30_GRF_SOC_STATUS0);

				   PX30_GRF_SOC_STATUS0);

drivers/clk/rockchip/clk-rk3228.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -110,6 +110,7 @@ static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { 
	RK3228_CPUCLK_RATE(1608000000, 1, 7),

	RK3228_CPUCLK_RATE(1608000000, 1, 7),

	RK3228_CPUCLK_RATE(1512000000, 1, 7),

	RK3228_CPUCLK_RATE(1512000000, 1, 7),

	RK3228_CPUCLK_RATE(1488000000, 1, 5),

	RK3228_CPUCLK_RATE(1488000000, 1, 5),

	RK3228_CPUCLK_RATE(1464000000, 1, 5),

	RK3228_CPUCLK_RATE(1416000000, 1, 5),

	RK3228_CPUCLK_RATE(1416000000, 1, 5),

	RK3228_CPUCLK_RATE(1392000000, 1, 5),

	RK3228_CPUCLK_RATE(1392000000, 1, 5),

	RK3228_CPUCLK_RATE(1296000000, 1, 5),

	RK3228_CPUCLK_RATE(1296000000, 1, 5),
@@ -255,7 +256,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 
			RK2928_CLKGATE_CON(4), 0, GFLAGS),

			RK2928_CLKGATE_CON(4), 0, GFLAGS),





	/* PD_MISC */

	/* PD_MISC */

	MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,

	MUX(SCLK_HDMI_PHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,

			RK2928_MISC_CON, 13, 1, MFLAGS),

			RK2928_MISC_CON, 13, 1, MFLAGS),

	MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,

	MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,

			RK2928_MISC_CON, 14, 1, MFLAGS),

			RK2928_MISC_CON, 14, 1, MFLAGS),

drivers/clk/rockchip/clk-rk3288.c

+3 −10
Original line number Original line Diff line number Diff line
@@ -122,7 +122,6 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { 
	RK3066_PLL_RATE( 160000000, 1, 80, 12),

	RK3066_PLL_RATE( 160000000, 1, 80, 12),

	RK3066_PLL_RATE( 157500000, 1, 105, 16),

	RK3066_PLL_RATE( 157500000, 1, 105, 16),

	RK3066_PLL_RATE( 126000000, 1, 84, 16),

	RK3066_PLL_RATE( 126000000, 1, 84, 16),

	RK3066_PLL_RATE(  48000000, 1, 64, 32),

	{ /* sentinel */ },

	{ /* sentinel */ },

};

};
@@ -776,6 +775,9 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 
	GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),

	GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),

	GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),

	GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),





	/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */

	SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),



	/* pclk_pd_pmu gates */

	/* pclk_pd_pmu gates */

	GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),

	GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),

	GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),

	GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
@@ -924,7 +926,6 @@ static struct syscore_ops rk3288_clk_syscore_ops = { 
static void __init rk3288_clk_init(struct device_node *np)

static void __init rk3288_clk_init(struct device_node *np)

{

{

	struct rockchip_clk_provider *ctx;

	struct rockchip_clk_provider *ctx;

	struct clk *clk;





	rk3288_cru_base = of_iomap(np, 0);

	rk3288_cru_base = of_iomap(np, 0);

	if (!rk3288_cru_base) {

	if (!rk3288_cru_base) {
@@ -939,14 +940,6 @@ static void __init rk3288_clk_init(struct device_node *np) 
		return;

		return;

	}

	}





	/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */

	clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);

	if (IS_ERR(clk))

		pr_warn("%s: could not register clock pclk_wdt: %ld\n",

			__func__, PTR_ERR(clk));

	else

		rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);



	rockchip_clk_register_plls(ctx, rk3288_pll_clks,

	rockchip_clk_register_plls(ctx, rk3288_pll_clks,

				   ARRAY_SIZE(rk3288_pll_clks),

				   ARRAY_SIZE(rk3288_pll_clks),

				   RK3288_GRF_SOC_STATUS1);

				   RK3288_GRF_SOC_STATUS1);

drivers/clk/rockchip/clk-rk3328.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -800,6 +800,9 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
	GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),

	GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),

	GATE(0, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 3, GFLAGS),

	GATE(0, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 3, GFLAGS),





	/* Watchdog pclk is controlled from the secure GRF */

	SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),



	GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS),

	GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS),

	GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS),

	GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS),

	GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),

	GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),

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