Commit 53e07424 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-actions', 'clk-rockchip', 'clk-iproc', 'clk-intel' and... 

Merge branches 'clk-actions', 'clk-rockchip', 'clk-iproc', 'clk-intel' and 'clk-debugfs' into clk-next

 - RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs

* clk-actions:
  MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs
  clk: actions: Add Actions S500 SoC Reset Management Unit support
  dt-bindings: reset: Add binding constants for Actions S500 RMU
  clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC
  dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC
  clk: actions: Fix h_clk for Actions S500 SoC

* clk-rockchip:
  clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks
  clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328"
  clk: rockchip: use separate compatibles for rk3288w-cru
  dt-bindings: clocks: add rk3288w variant compatible
  clk: rockchip: Handle clock tree for rk3288w variant
  clk: rockchip: convert rk3036 pll type to use internal lock status
  clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeout
  clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeout

* clk-iproc:
  clk: iproc: round clock rate to the closest

* clk-intel:
  clk: intel: Avoid unnecessary memset by improving code
  clk: intel: Improve locking in the driver
  clk: intel: Use devm_clk_hw_register() instead of clk_hw_register()

* clk-debugfs:
  clk: Add support for enabling/disabling clocks from debugfs
parents 987106e5 cb7c6677 aab58ace 9f7d5042 d310124c 03111b10

Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt

+7 −1
Original line number Diff line number Diff line
@@ -4,9 +4,15 @@ The RK3288 clock controller generates and supplies clock to various 
controllers within the SoC and also implements a reset controller for SoC

peripherals.



A revision of this SoC is available: rk3288w. The clock tree is a bit

different so another dt-compatible is available. Noticed that it is only

setting the difference but there is no automatic revision detection. This

should be performed by bootloaders.



Required Properties:



- compatible: should be "rockchip,rk3288-cru"

- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in

  case of this revision of Rockchip rk3288.

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -1533,6 +1533,7 @@ F: drivers/mmc/host/owl-mmc.c 
F:	drivers/pinctrl/actions/*

F:	drivers/soc/actions/

F:	include/dt-bindings/power/owl-*

F:	include/dt-bindings/reset/actions,*

F:	include/linux/soc/actions/

N:	owl

































drivers/clk/actions/owl-s500.c



+88
−1






























Original line number
Diff line number
Diff line








@@ -23,8 +23,10 @@













#include "owl-gate.h"















#include "owl-mux.h"















#include "owl-pll.h"













#include "owl-reset.h"































#include <dt-bindings/clock/actions,s500-cmu.h>













#include <dt-bindings/reset/actions,s500-reset.h>































#define CMU_COREPLL			(0x0000)















#define CMU_DEVPLL			(0x0004)










@@ -175,6 +177,8 @@ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RAT













static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);































/* gate clocks */













static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);













static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);















static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);















static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);















static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);









@@ -183,7 +187,8 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);













static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);































/* divider clocks */













static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);













static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);













static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);















static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);































/* factor clocks */










@@ -428,6 +433,9 @@ static struct owl_clk_common *s500_clks[] = {













	&spdif_clk.common,















	&nand_clk.common,















	&ecc_clk.common,













	&apb_clk.common,













	&dmac_clk.common,













	&gpio_clk.common,















};































static struct clk_hw_onecell_data s500_hw_clks = {










@@ -484,24 +492,103 @@ static struct clk_hw_onecell_data s500_hw_clks = {













		[CLK_SPDIF]		= &spdif_clk.common.hw,















		[CLK_NAND]		= &nand_clk.common.hw,















		[CLK_ECC]		= &ecc_clk.common.hw,













		[CLK_APB]		= &apb_clk.common.hw,













		[CLK_DMAC]		= &dmac_clk.common.hw,













		[CLK_GPIO]		= &gpio_clk.common.hw,















	},















	.num = CLK_NR_CLKS,















};





























static const struct owl_reset_map s500_resets[] = {













	[RESET_DMAC]	= { CMU_DEVRST0, BIT(0) },













	[RESET_NORIF]	= { CMU_DEVRST0, BIT(1) },













	[RESET_DDR]	= { CMU_DEVRST0, BIT(2) },













	[RESET_NANDC]	= { CMU_DEVRST0, BIT(3) },













	[RESET_SD0]	= { CMU_DEVRST0, BIT(4) },













	[RESET_SD1]	= { CMU_DEVRST0, BIT(5) },













	[RESET_PCM1]	= { CMU_DEVRST0, BIT(6) },













	[RESET_DE]	= { CMU_DEVRST0, BIT(7) },













	[RESET_LCD]	= { CMU_DEVRST0, BIT(8) },













	[RESET_SD2]	= { CMU_DEVRST0, BIT(9) },













	[RESET_DSI]	= { CMU_DEVRST0, BIT(10) },













	[RESET_CSI]	= { CMU_DEVRST0, BIT(11) },













	[RESET_BISP]	= { CMU_DEVRST0, BIT(12) },













	[RESET_KEY]	= { CMU_DEVRST0, BIT(14) },













	[RESET_GPIO]	= { CMU_DEVRST0, BIT(15) },













	[RESET_AUDIO]	= { CMU_DEVRST0, BIT(17) },













	[RESET_PCM0]	= { CMU_DEVRST0, BIT(18) },













	[RESET_VDE]	= { CMU_DEVRST0, BIT(19) },













	[RESET_VCE]	= { CMU_DEVRST0, BIT(20) },













	[RESET_GPU3D]	= { CMU_DEVRST0, BIT(22) },













	[RESET_NIC301]	= { CMU_DEVRST0, BIT(23) },













	[RESET_LENS]	= { CMU_DEVRST0, BIT(26) },













	[RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },













	[RESET_USB2_0]	= { CMU_DEVRST1, BIT(0) },













	[RESET_TVOUT]	= { CMU_DEVRST1, BIT(1) },













	[RESET_HDMI]	= { CMU_DEVRST1, BIT(2) },













	[RESET_HDCP2TX]	= { CMU_DEVRST1, BIT(3) },













	[RESET_UART6]	= { CMU_DEVRST1, BIT(4) },













	[RESET_UART0]	= { CMU_DEVRST1, BIT(5) },













	[RESET_UART1]	= { CMU_DEVRST1, BIT(6) },













	[RESET_UART2]	= { CMU_DEVRST1, BIT(7) },













	[RESET_SPI0]	= { CMU_DEVRST1, BIT(8) },













	[RESET_SPI1]	= { CMU_DEVRST1, BIT(9) },













	[RESET_SPI2]	= { CMU_DEVRST1, BIT(10) },













	[RESET_SPI3]	= { CMU_DEVRST1, BIT(11) },













	[RESET_I2C0]	= { CMU_DEVRST1, BIT(12) },













	[RESET_I2C1]	= { CMU_DEVRST1, BIT(13) },













	[RESET_USB3]	= { CMU_DEVRST1, BIT(14) },













	[RESET_UART3]	= { CMU_DEVRST1, BIT(15) },













	[RESET_UART4]	= { CMU_DEVRST1, BIT(16) },













	[RESET_UART5]	= { CMU_DEVRST1, BIT(17) },













	[RESET_I2C2]	= { CMU_DEVRST1, BIT(18) },













	[RESET_I2C3]	= { CMU_DEVRST1, BIT(19) },













	[RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },













	[RESET_CHIPID]	= { CMU_DEVRST1, BIT(21) },













	[RESET_USB2_1]	= { CMU_DEVRST1, BIT(22) },













	[RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },













	[RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },













	[RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },













	[RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },













	[RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },













	[RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },













	[RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },













	[RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },













};





























static struct owl_clk_desc s500_clk_desc = {















	.clks	    = s500_clks,















	.num_clks   = ARRAY_SIZE(s500_clks),































	.hw_clks    = &s500_hw_clks,



























	.resets     = s500_resets,













	.num_resets = ARRAY_SIZE(s500_resets),















};































static int s500_clk_probe(struct platform_device *pdev)















{















	struct owl_clk_desc *desc;













	struct owl_reset *reset;













	int ret;































	desc = &s500_clk_desc;















	owl_clk_regmap_init(pdev, desc);





























	reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);













	if (!reset)













		return -ENOMEM;



























	reset->rcdev.of_node = pdev->dev.of_node;













	reset->rcdev.ops = &owl_reset_ops;













	reset->rcdev.nr_resets = desc->num_resets;













	reset->reset_map = desc->resets;













	reset->regmap = desc->regmap;



























	ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);













	if (ret)













		dev_err(&pdev->dev, "Failed to register reset controller\n");





























	return owl_clk_probe(&pdev->dev, desc->hw_clks);















}

















































drivers/clk/bcm/clk-iproc-asiu.c



+2
−2






























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@@ -119,7 +119,7 @@ static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,













	if (rate == *parent_rate)















		return *parent_rate;





























	div = DIV_ROUND_UP(*parent_rate, rate);













	div = DIV_ROUND_CLOSEST(*parent_rate, rate);















	if (div < 2)















		return *parent_rate;

























@@ -145,7 +145,7 @@ static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,













		return 0;















	}





























	div = DIV_ROUND_UP(parent_rate, rate);













	div = DIV_ROUND_CLOSEST(parent_rate, rate);















	if (div < 2)















		return -EINVAL;

















































drivers/clk/clk.c



+29
−0






























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Diff line








@@ -3054,6 +3054,31 @@ static int clk_rate_set(void *data, u64 val)













}































#define clk_rate_mode	0644



























static int clk_prepare_enable_set(void *data, u64 val)













{













	struct clk_core *core = data;













	int ret = 0;



























	if (val)













		ret = clk_prepare_enable(core->hw->clk);













	else













		clk_disable_unprepare(core->hw->clk);



























	return ret;













}



























static int clk_prepare_enable_get(void *data, u64 *val)













{













	struct clk_core *core = data;



























	*val = core->enable_count && core->prepare_count;













	return 0;













}



























DEFINE_DEBUGFS_ATTRIBUTE(clk_prepare_enable_fops, clk_prepare_enable_get,













			 clk_prepare_enable_set, "%llu\n");





























#else















#define clk_rate_set	NULL















#define clk_rate_mode	0444










@@ -3231,6 +3256,10 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)













	debugfs_create_u32("clk_notifier_count", 0444, root, &core->notifier_count);















	debugfs_create_file("clk_duty_cycle", 0444, root, core,















			    &clk_duty_cycle_fops);













#ifdef CLOCK_ALLOW_WRITE_DEBUGFS













	debugfs_create_file("clk_prepare_enable", 0644, root, core,













			    &clk_prepare_enable_fops);













#endif































	if (core->num_parents > 0)















		debugfs_create_file("clk_parent", 0444, root, core,









































































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