Commit 53a2cc5c authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-ti', 'clk-ingenic', 'clk-typo', 'clk-at91', 'clk-mmp2' and... 

Merge branches 'clk-ti', 'clk-ingenic', 'clk-typo', 'clk-at91', 'clk-mmp2' and 'clk-arm-icst' into clk-next

 - EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs
 - Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs
 - Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers

* clk-ti:
  clk: keystone: Add new driver to handle syscon based clocks
  dt-bindings: clock: Add binding documentation for TI EHRPWM TBCLK

* clk-ingenic:
  clk: ingenic/TCU: Fix round_rate returning error
  clk: ingenic/jz4770: Exit with error if CGU init failed
  clk: JZ4780: Add function for enable the second core.
  clk: Ingenic: Add support for TCU of X1000.

* clk-typo:
  clk: Fix trivia typo in comment exlusive => exclusive

* clk-at91:
  clk: at91: add at91rm9200 pmc driver
  clk: at91: add at91sam9n12 pmc driver
  clk: at91: add sama5d3 pmc driver
  clk: at91: add at91sam9g45 pmc driver
  clk: at91: usb: introduce num_parents in driver's structure
  clk: at91: usb: use proper usbs_mask
  clk: at91: sam9x60: fix usb clock parents
  clk: at91: usb: continue if clk_hw_round_rate() return zero
  clk: at91: sam9x60: Don't use audio PLL

* clk-mmp2:
  clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks
  clk: mmp2: Add clock for fifth SD HCI on MMP3
  dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3
  clk: mmp2: Add clocks for the thermal sensors
  dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors
  clk: mmp2: add the GPU clocks
  dt-bindings: marvell,mmp2: Add clock ids for the GPU clocks
  clk: mmp2: Add PLLs that are available on MMP3
  dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs
  clk: mmp2: Check for MMP3
  dt-bindings: clock: Add MMP3 compatible string
  clk: mmp2: Stop pretending PLL outputs are constant
  clk: mmp2: Add support for PLL clock sources
  dt-bindings: clock: Convert marvell,mmp2-clock to json-schema
  clk: mmp2: Constify some strings
  clk: mmp2: Remove a unused prototype

* clk-arm-icst:
  MAINTAINERS: dt: update reference for arm-integrator.txt
  clk: versatile: Add device tree probing for IM-PD1 clocks
  clk: versatile: Export icst_clk_setup()
  dt-bindings: clock: Create YAML schema for ICST clocks
parents 2d11e9a1 1aa0817e edcc4294 a37a5a9d 02ff48e4 de17be99 7928f4f6

Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM System Controller ICST Clocks



maintainers:

  - Linus Walleij <linusw@kernel.org>



description: |

  The ICS525 and ICS307 oscillators are produced by Integrated

  Devices Technology (IDT). ARM integrated these oscillators deeply into their

  reference designs by adding special control registers that manage such

  oscillators to their system controllers.



  The various ARM system controllers contain logic to serialize and initialize

  an ICST clock request after a write to the 32 bit register at an offset

  into the system controller. Furthermore, to even be able to alter one of

  these frequencies, the system controller must first be unlocked by

  writing a special token to another offset in the system controller.



  Some ARM hardware contain special versions of the serial interface that only

  connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to

  different values and sometimes also hard-wires the output divider. They

  therefore have special compatible strings as per this table (the OD value is

  the value on the pins, not the resulting output divider).



  In the core modules and logic tiles, the ICST is a configurable clock fed

  from a 24 MHz clock on the motherboard (usually the main crystal) used for

  generating e.g. video clocks. It is located on the core module and there is

  only one of these. This clock node must be a subnode of the core module.



  Hardware variant         RDW     OD          VDW



  Integrator/AP            22      1           Bit 8 0, rest variable

  integratorap-cm



  Integrator/AP            46      3           Bit 8 0, rest variable

  integratorap-sys



  Integrator/AP            22 or   1           17 or (33 or 25 MHz)

  integratorap-pci         14      1           14



  Integrator/CP            22      variable    Bit 8 0, rest variable

  integratorcp-cm-core



  Integrator/CP            22      variable    Bit 8 0, rest variable

  integratorcp-cm-mem



  The ICST oscillator must be provided inside a system controller node.



properties:

  "#clock-cells":

    const: 0



  compatible:

    enum:

      - arm,syscon-icst525

      - arm,syscon-icst307

      - arm,syscon-icst525-integratorap-cm

      - arm,syscon-icst525-integratorap-sys

      - arm,syscon-icst525-integratorap-pci

      - arm,syscon-icst525-integratorcp-cm-core

      - arm,syscon-icst525-integratorcp-cm-mem

      - arm,integrator-cm-auxosc

      - arm,versatile-cm-auxosc

      - arm,impd-vco1

      - arm,impd-vco2



  clocks:

    description: Parent clock for the ICST VCO

    maxItems: 1



  clock-output-names:

    maxItems: 1



  lock-offset:

    $ref: '/schemas/types.yaml#/definitions/uint32'

    description: Offset to the unlocking register for the oscillator



  vco-offset:

    $ref: '/schemas/types.yaml#/definitions/uint32'

    description: Offset to the VCO register for the oscillator



required:

  - "#clock-cells"

  - compatible

  - clocks



examples:

  - |

    vco1: clock@00 {

      compatible = "arm,impd1-vco1";

      #clock-cells = <0>;

      lock-offset = <0x08>;

      vco-offset = <0x00>;

      clocks = <&sysclk>;

      clock-output-names = "IM-PD1-VCO1";

    };



...

Documentation/devicetree/bindings/clock/arm-integrator.txt

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Clock bindings for ARM Integrator and Versatile Core Module clocks



Auxiliary Oscillator Clock



This is a configurable clock fed from a 24 MHz chrystal,

used for generating e.g. video clocks. It is located on the

core module and there is only one of these.



This clock node *must* be a subnode of the core module, since

it obtains the base address for it's address range from its

parent node.





Required properties:

- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc"

- #clock-cells: must be <0>



Optional properties:

- clocks: parent clock(s)



Example:



core-module@10000000 {

	xtal24mhz: xtal24mhz@24M {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		clock-frequency = <24000000>;

	};

	auxosc: cm_aux_osc@25M {

		#clock-cells = <0>;

		compatible = "arm,integrator-cm-auxosc";

		clocks = <&xtal24mhz>;

	};

};

Documentation/devicetree/bindings/clock/arm-syscon-icst.txt

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ARM System Controller ICST clocks



The ICS525 and ICS307 oscillators are produced by Integrated Devices

Technology (IDT). ARM integrated these oscillators deeply into their

reference designs by adding special control registers that manage such

oscillators to their system controllers.



The various ARM system controllers contain logic to serialize and initialize

an ICST clock request after a write to the 32 bit register at an offset

into the system controller. Furthermore, to even be able to alter one of

these frequencies, the system controller must first be unlocked by

writing a special token to another offset in the system controller.



Some ARM hardware contain special versions of the serial interface that only

connects the low 8 bits of the VDW (missing one bit), hardwires RDW to

different values and sometimes also hardwire the output divider. They

therefore have special compatible strings as per this table (the OD value is

the value on the pins, not the resulting output divider):



Hardware variant:        RDW     OD          VDW



Integrator/AP            22      1           Bit 8 0, rest variable

integratorap-cm



Integrator/AP            46      3           Bit 8 0, rest variable

integratorap-sys



Integrator/AP            22 or   1           17 or (33 or 25 MHz)

integratorap-pci         14      1           14



Integrator/CP            22      variable    Bit 8 0, rest variable

integratorcp-cm-core



Integrator/CP            22      variable    Bit 8 0, rest variable

integratorcp-cm-mem



The ICST oscillator must be provided inside a system controller node.



Required properties:

- compatible: must be one of

  "arm,syscon-icst525"

  "arm,syscon-icst307"

  "arm,syscon-icst525-integratorap-cm"

  "arm,syscon-icst525-integratorap-sys"

  "arm,syscon-icst525-integratorap-pci"

  "arm,syscon-icst525-integratorcp-cm-core"

  "arm,syscon-icst525-integratorcp-cm-mem"

- lock-offset: the offset address into the system controller where the

  unlocking register is located

- vco-offset: the offset address into the system controller where the

  ICST control register is located (even 32 bit address)

- #clock-cells: must be <0>

- clocks: parent clock, since the ICST needs a parent clock to derive its

  frequency from, this attribute is compulsory.



Example:



syscon: syscon@10000000 {

	compatible = "syscon";

	reg = <0x10000000 0x1000>;



	oscclk0: osc0@c {

		compatible = "arm,syscon-icst307";

		#clock-cells = <0>;

		lock-offset = <0x20>;

		vco-offset = <0x0c>;

		clocks = <&xtal24mhz>;

	};

	(...)

};

Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Marvell MMP2 and MMP3 Clock Controller



maintainers:

  - Lubomir Rintel <lkundrak@v3.sk>



description: |

  The clock subsystem on MMP2 or MMP3 generates and supplies clock to various

  controllers within the SoC.



  Each clock is assigned an identifier and client nodes use this identifier

  to specify the clock which they consume.



  All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.



properties:

  compatible:

    enum:

      - marvell,mmp2-clock # controller compatible with MMP2 SoC

      - marvell,mmp3-clock # controller compatible with MMP3 SoC



  reg:

    items:

      - description: MPMU register region

      - description: APMU register region

      - description: APBC register region



  reg-names:

    items:

      - const: mpmu

      - const: apmu

      - const: apbc



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



required:

  - compatible

  - reg

  - reg-names

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    clock-controller@d4050000 {

      compatible = "marvell,mmp2-clock";

      reg = <0xd4050000 0x1000>,

            <0xd4282800 0x400>,

            <0xd4015000 0x1000>;

      reg-names = "mpmu", "apmu", "apbc";

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/marvell,mmp2.txt

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* Marvell MMP2 Clock Controller



The MMP2 clock subsystem generates and supplies clock to various

controllers within the MMP2 SoC.



Required Properties:



- compatible: should be one of the following.

  - "marvell,mmp2-clock" - controller compatible with MMP2 SoC.



- reg: physical base address of the clock subsystem and length of memory mapped

  region. There are 3 places in SOC has clock control logic:

  "mpmu", "apmu", "apbc". So three reg spaces need to be defined.



- #clock-cells: should be 1.

- #reset-cells: should be 1.



Each clock is assigned an identifier and client nodes use this identifier

to specify the clock which they consume.



All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.

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