Commit 538fdf1f authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: move macros to hwmgr.h 



the macro is not relevant to SMU,
so rename SMU_WAIT_FIELD_UNEQUAL to
PHM_WAIT_FIELD_UNEQUAL and move to hwmgr.h

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 57d13f79

drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

+14 −0
Original line number Diff line number Diff line
@@ -929,4 +929,18 @@ extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_t 
		(fieldval) << PHM_FIELD_SHIFT(reg, field),		\

		PHM_FIELD_MASK(reg, field))



#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,         \

							index, value, mask) \

		phm_wait_for_register_unequal(hwmgr,            \

					index, value, mask)



#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask)		\

	PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,			\

				mm##reg, value, mask)



#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval)		\

	PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg,				\

		(fieldval) << PHM_FIELD_SHIFT(reg, field),		\

		PHM_FIELD_MASK(reg, field))



#endif /* _HWMGR_H_ */

drivers/gpu/drm/amd/powerplay/inc/smumgr.h

+0 −14
Original line number Diff line number Diff line
@@ -163,20 +163,6 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr); 
	    SMUM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \

			            SMUM_FIELD_MASK(reg, field) )



#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,         \

							index, value, mask) \

		smum_wait_for_register_unequal(hwmgr,            \

					index, value, mask)



#define SMUM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask)		\

	SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,			\

				mm##reg, value, mask)



#define SMUM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval)		\

	SMUM_WAIT_REGISTER_UNEQUAL(hwmgr, reg,				\

		(fieldval) << SMUM_FIELD_SHIFT(reg, field),		\

		SMUM_FIELD_MASK(reg, field))



#define SMUM_GET_FIELD(value, reg, field)				\

		(((value) & SMUM_FIELD_MASK(reg, field))		\

		>> SMUM_FIELD_SHIFT(reg, field))

drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c

+1 −1
Original line number Diff line number Diff line
@@ -217,7 +217,7 @@ int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) 


	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);



	SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);

	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);



	ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);

drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c

+2 −2
Original line number Diff line number Diff line
@@ -68,7 +68,7 @@ static int cz_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg) 
	if (hwmgr == NULL || hwmgr->device == NULL)

		return -EINVAL;



	result = SMUM_WAIT_FIELD_UNEQUAL(hwmgr,

	result = PHM_WAIT_FIELD_UNEQUAL(hwmgr,

					SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);

	if (result != 0) {

		pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg);
@@ -90,7 +90,7 @@ static int cz_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) 
	if (result != 0)

		return result;



	return SMUM_WAIT_FIELD_UNEQUAL(hwmgr,

	return PHM_WAIT_FIELD_UNEQUAL(hwmgr,

					SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);

}

drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c

+1 −1
Original line number Diff line number Diff line
@@ -101,7 +101,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) 


	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);

	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);

	SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);

	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);



	/* Wait for done bit to be set */

	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,

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