Commit 57d13f79 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: move PHM_WAIT_VFPF_INDIRECT_FIELD to hwmgr.h 



the macro is not relevant to SMU, so move to hwmgr.h
and rename to PHM_WAIT_VFPF_INDIRECT_FIELD

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 554d95da

drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

+14 −0
Original line number Diff line number Diff line
@@ -915,4 +915,18 @@ extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_t 
		(fieldval) << PHM_FIELD_SHIFT(reg, field),		\

		PHM_FIELD_MASK(reg, field))





#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr,		\

				port, index, value, mask)		\

	phm_wait_on_indirect_register(hwmgr,				\

		mm##port##_INDEX_11, index, value, mask)



#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \

	PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)



#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \

	PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg,		\

		(fieldval) << PHM_FIELD_SHIFT(reg, field),		\

		PHM_FIELD_MASK(reg, field))



#endif /* _HWMGR_H_ */

drivers/gpu/drm/amd/powerplay/inc/smumgr.h

+1 −13
Original line number Diff line number Diff line
@@ -193,17 +193,8 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr); 
	    SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \

			   reg, field)



#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr,		\

				port, index, value, mask)		\

	smum_wait_on_indirect_register(hwmgr,				\

		mm##port##_INDEX_11, index, value, mask)









#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \

	SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
@@ -229,10 +220,7 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr); 
				       reg, field, fieldval))





#define SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \

	SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg,		\

		(fieldval) << SMUM_FIELD_SHIFT(reg, field),		\

		SMUM_FIELD_MASK(reg, field))







#endif

drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c

+3 −3
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) 
	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,

			ixFIRMWARE_FLAGS, 0);



	SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,

	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,

			INTERRUPTS_ENABLED, 1);



	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
@@ -115,7 +115,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) 
	}



	/* Wait for firmware to initialize */

	SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,

	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,

			FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);



	return result;
@@ -153,7 +153,7 @@ static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr) 
			SMC_SYSCON_RESET_CNTL, rst_reg, 0);



	/* Wait for firmware to initialize */

	SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,

	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,

			FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);



	return result;

drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c

+3 −3
Original line number Diff line number Diff line
@@ -241,7 +241,7 @@ static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) 
					SMC_SYSCON_RESET_CNTL, rst_reg, 0);





	SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);

	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);





	/* Call Test SMU message with 0x20000 offset to trigger SMU start */
@@ -265,7 +265,7 @@ static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) 
					SMC_SYSCON_RESET_CNTL, rst_reg, 0);



	/* Wait for firmware to initialize */

	SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);

	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);



	return result;

}
@@ -301,7 +301,7 @@ static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr) 


	/* Wait for firmware to initialize */



	SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,

	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,

					FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);



	return result;

drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c

+1 −1
Original line number Diff line number Diff line
@@ -235,7 +235,7 @@ int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr) 
	if (!smu7_is_smc_ram_running(hwmgr))

		return -EINVAL;



	SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);

	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);

	return 0;

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE